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| author | Tim Hatch <tim@timhatch.com> | 2012-02-27 18:55:15 -0800 |
|---|---|---|
| committer | Tim Hatch <tim@timhatch.com> | 2012-02-27 18:55:15 -0800 |
| commit | 9d519e510f887c337c7a715d80e07b15357d33dc (patch) | |
| tree | 5d847cc5a55354f5494d67c1e5034891f3b244c2 /pygments/lexers/hdl.py | |
| parent | 5558d3ba11cc7b2d1e16228ce3c5402b7d48072c (diff) | |
| parent | e6abbe90c96cb77c0a775c8ae4427eb2f49c1f98 (diff) | |
| download | pygments-9d519e510f887c337c7a715d80e07b15357d33dc.tar.gz | |
Merge pygments-main with pygments-tim
Diffstat (limited to 'pygments/lexers/hdl.py')
| -rw-r--r-- | pygments/lexers/hdl.py | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/pygments/lexers/hdl.py b/pygments/lexers/hdl.py index b4eccd3b..86534b76 100644 --- a/pygments/lexers/hdl.py +++ b/pygments/lexers/hdl.py @@ -75,21 +75,21 @@ class VerilogLexer(RegexLexer): r'unsigned|var|vectored|void|wait|weak0|weak1|while|' r'xnor|xor)\b', Keyword), - (r'(`accelerate|`autoexpand_vectornets|`celldefine|`default_nettype|' - r'`else|`elsif|`endcelldefine|`endif|`endprotect|`endprotected|' - r'`expand_vectornets|`ifdef|`ifndef|`include|`noaccelerate|`noexpand_vectornets|' - r'`noremove_gatenames|`noremove_netnames|`nounconnected_drive|' - r'`protect|`protected|`remove_gatenames|`remove_netnames|`resetall|' - r'`timescale|`unconnected_drive|`undef)\b', Comment.Preproc), - - (r'(\$bits|\$bitstoreal|\$bitstoshortreal|\$countdrivers|\$display|\$fclose|' - r'\$fdisplay|\$finish|\$floor|\$fmonitor|\$fopen|\$fstrobe|\$fwrite|' - r'\$getpattern|\$history|\$incsave|\$input|\$itor|\$key|\$list|\$log|' - r'\$monitor|\$monitoroff|\$monitoron|\$nokey|\$nolog|\$printtimescale|' - r'\$random|\$readmemb|\$readmemh|\$realtime|\$realtobits|\$reset|\$reset_count|' - r'\$reset_value|\$restart|\$rtoi|\$save|\$scale|\$scope|\$shortrealtobits|' - r'\$showscopes|\$showvariables|\$showvars|\$sreadmemb|\$sreadmemh|' - r'\$stime|\$stop|\$strobe|\$time|\$timeformat|\$write)\b', Name.Builtin), + (r'`(accelerate|autoexpand_vectornets|celldefine|default_nettype|' + r'else|elsif|endcelldefine|endif|endprotect|endprotected|' + r'expand_vectornets|ifdef|ifndef|include|noaccelerate|noexpand_vectornets|' + r'noremove_gatenames|noremove_netnames|nounconnected_drive|' + r'protect|protected|remove_gatenames|remove_netnames|resetall|' + r'timescale|unconnected_drive|undef)\b', Comment.Preproc), + + (r'\$(bits|bitstoreal|bitstoshortreal|countdrivers|display|fclose|' + r'fdisplay|finish|floor|fmonitor|fopen|fstrobe|fwrite|' + r'getpattern|history|incsave|input|itor|key|list|log|' + r'monitor|monitoroff|monitoron|nokey|nolog|printtimescale|' + r'random|readmemb|readmemh|realtime|realtobits|reset|reset_count|' + r'reset_value|restart|rtoi|save|scale|scope|shortrealtobits|' + r'showscopes|showvariables|showvars|sreadmemb|sreadmemh|' + r'stime|stop|strobe|time|timeformat|write)\b', Name.Builtin), (r'(byte|shortint|int|longint|integer|time|' r'bit|logic|reg|' |