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| author | Georg Brandl <georg@python.org> | 2016-02-02 12:43:03 +0100 |
|---|---|---|
| committer | Georg Brandl <georg@python.org> | 2016-02-02 12:43:03 +0100 |
| commit | 37d2f0ab87220f2e15b9553501721e21e5356fe1 (patch) | |
| tree | 3e25c4ac32ed54fcb92139f66875596a4a1d7c88 /pygments | |
| parent | 493c0afaf6b7abd79cc48f6221c97ca9524ddd5d (diff) | |
| download | pygments-37d2f0ab87220f2e15b9553501721e21e5356fe1.tar.gz | |
VHDL updates (closes #1177)
Diffstat (limited to 'pygments')
| -rw-r--r-- | pygments/lexers/hdl.py | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/pygments/lexers/hdl.py b/pygments/lexers/hdl.py index 8fb1fb43..04cef14e 100644 --- a/pygments/lexers/hdl.py +++ b/pygments/lexers/hdl.py @@ -308,20 +308,27 @@ class VhdlLexer(RegexLexer): (r'[~!%^&*+=|?:<>/-]', Operator), (r"'[a-z_]\w*", Name.Attribute), (r'[()\[\],.;\']', Punctuation), - (r'"[^\n\\]*"', String), + (r'"[^\n\\"]*"', String), (r'(library)(\s+)([a-z_]\w*)', bygroups(Keyword, Text, Name.Namespace)), (r'(use)(\s+)(entity)', bygroups(Keyword, Text, Keyword)), + (r'(use)(\s+)([a-z_][\w.]*\.)(all)', + bygroups(Keyword, Text, Name.Namespace, Keyword)), (r'(use)(\s+)([a-z_][\w.]*)', bygroups(Keyword, Text, Name.Namespace)), + (r'(std|ieee)(\.[a-z_]\w*)', + bygroups(Name.Namespace, Name.Namespace)), + (words(('std', 'ieee', 'work'), suffix=r'\b'), + Name.Namespace), (r'(entity|component)(\s+)([a-z_]\w*)', bygroups(Keyword, Text, Name.Class)), (r'(architecture|configuration)(\s+)([a-z_]\w*)(\s+)' r'(of)(\s+)([a-z_]\w*)(\s+)(is)', bygroups(Keyword, Text, Name.Class, Text, Keyword, Text, Name.Class, Text, Keyword)), - + (r'([a-z_]\w*)(:)(\s+)(process|for)', + bygroups(Name.Class, Operator, Text, Keyword)), (r'(end)(\s+)', bygroups(using(this), Text), 'endblock'), include('types'), @@ -341,7 +348,7 @@ class VhdlLexer(RegexLexer): 'boolean', 'bit', 'character', 'severity_level', 'integer', 'time', 'delay_length', 'natural', 'positive', 'string', 'bit_vector', 'file_open_kind', 'file_open_status', 'std_ulogic', 'std_ulogic_vector', - 'std_logic', 'std_logic_vector'), suffix=r'\b'), + 'std_logic', 'std_logic_vector', 'signed', 'unsigned'), suffix=r'\b'), Keyword.Type), ], 'keywords': [ @@ -357,8 +364,8 @@ class VhdlLexer(RegexLexer): 'next', 'nor', 'not', 'null', 'of', 'on', 'open', 'or', 'others', 'out', 'package', 'port', 'postponed', 'procedure', 'process', 'pure', 'range', 'record', - 'register', 'reject', 'return', 'rol', 'ror', 'select', - 'severity', 'signal', 'shared', 'sla', 'sli', 'sra', + 'register', 'reject', 'rem', 'return', 'rol', 'ror', 'select', + 'severity', 'signal', 'shared', 'sla', 'sll', 'sra', 'srl', 'subtype', 'then', 'to', 'transport', 'type', 'units', 'until', 'use', 'variable', 'wait', 'when', 'while', 'with', 'xnor', 'xor'), suffix=r'\b'), |