diff options
Diffstat (limited to 'pygments/lexers/hdl.py')
| -rw-r--r-- | pygments/lexers/hdl.py | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/pygments/lexers/hdl.py b/pygments/lexers/hdl.py index 0db35e74..1ebe4e5c 100644 --- a/pygments/lexers/hdl.py +++ b/pygments/lexers/hdl.py @@ -5,7 +5,7 @@ Lexers for hardware descriptor languages. - :copyright: Copyright 2006-2012 by the Pygments team, see AUTHORS. + :copyright: Copyright 2006-2014 by the Pygments team, see AUTHORS. :license: BSD, see LICENSE for details. """ @@ -22,10 +22,10 @@ class VerilogLexer(RegexLexer): """ For verilog source code with preprocessor directives. - *New in Pygments 1.4.* + .. versionadded:: 1.4 """ name = 'verilog' - aliases = ['v'] + aliases = ['verilog', 'v'] filenames = ['*.v'] mimetypes = ['text/x-verilog'] @@ -134,10 +134,10 @@ class SystemVerilogLexer(RegexLexer): Extends verilog lexer to recognise all SystemVerilog keywords from IEEE 1800-2009 standard. - *New in Pygments 1.5.* + .. versionadded:: 1.5 """ name = 'systemverilog' - aliases = ['sv'] + aliases = ['systemverilog', 'sv'] filenames = ['*.sv', '*.svh'] mimetypes = ['text/x-systemverilog'] @@ -215,12 +215,12 @@ class SystemVerilogLexer(RegexLexer): r'\$dumpportsall|\$dumpportsflush|\$dumpportslimit|\$dumpportsoff|' r'\$dumpportson|\$dumpvars|\$fclose|\$fdisplay|\$fdisplayb|' r'\$fdisplayh|\$fdisplayo|\$feof|\$ferror|\$fflush|\$fgetc|' - r'\$fgets|\$fmonitor|\$fmonitorb|\$fmonitorh|\$fmonitoro|' + r'\$fgets|\$finish|\$fmonitor|\$fmonitorb|\$fmonitorh|\$fmonitoro|' r'\$fopen|\$fread|\$fscanf|\$fseek|\$fstrobe|\$fstrobeb|\$fstrobeh|' r'\$fstrobeo|\$ftell|\$fwrite|\$fwriteb|\$fwriteh|\$fwriteo|' r'\$monitor|\$monitorb|\$monitorh|\$monitoro|\$monitoroff|' - r'\$monitoron|\$plusargs|\$readmemb|\$readmemh|\$rewind|\$sformat|' - r'\$sformatf|\$sscanf|\$strobe|\$strobeb|\$strobeh|\$strobeo|' + r'\$monitoron|\$plusargs|\$random\|$readmemb|\$readmemh|\$rewind|' + r'\$sformat|\$sformatf|\$sscanf|\$strobe|\$strobeb|\$strobeh|\$strobeo|' r'\$swrite|\$swriteb|\$swriteh|\$swriteo|\$test|\$ungetc|' r'\$value\$plusargs|\$write|\$writeb|\$writeh|\$writememb|' r'\$writememh|\$writeo)\b' , Name.Builtin ), @@ -274,7 +274,7 @@ class VhdlLexer(RegexLexer): """ For VHDL source code. - *New in Pygments 1.5.* + .. versionadded:: 1.5 """ name = 'vhdl' aliases = ['vhdl'] |