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| author | Sylvain Th?nault <sylvain.thenault@logilab.fr> | 2013-12-22 23:41:57 +0100 |
|---|---|---|
| committer | Sylvain Th?nault <sylvain.thenault@logilab.fr> | 2013-12-22 23:41:57 +0100 |
| commit | d8895fcb65ecd958b627298b32b0592565ef137e (patch) | |
| tree | 57cdbc1a28493d1f131fa2b4a8a3ff6611c7fa2b /checkers/design_analysis.py | |
| parent | d3f5227f8903cf72d7de78d0c2a9fc2948b19ca9 (diff) | |
| download | pylint-d8895fcb65ecd958b627298b32b0592565ef137e.tar.gz | |
various pylint fixes
Diffstat (limited to 'checkers/design_analysis.py')
| -rw-r--r-- | checkers/design_analysis.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/checkers/design_analysis.py b/checkers/design_analysis.py index ca201f3..11defbf 100644 --- a/checkers/design_analysis.py +++ b/checkers/design_analysis.py @@ -332,7 +332,7 @@ class MisdesignChecker(BaseChecker): """increments the branches counter""" branches = 1 # don't double count If nodes coming from some 'elif' - if node.orelse and (len(node.orelse)>1 or + if node.orelse and (len(node.orelse) > 1 or not isinstance(node.orelse[0], If)): branches += 1 self._inc_branch(branches) |