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author | cliechti <cliechti@f19166aa-fa4f-0410-85c2-fa1106f25c8a> | 2009-08-03 23:49:02 +0000 |
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committer | cliechti <cliechti@f19166aa-fa4f-0410-85c2-fa1106f25c8a> | 2009-08-03 23:49:02 +0000 |
commit | 7fc7da0d5a52eb4b3c0d5b9abafafb14dbd1281e (patch) | |
tree | d39dd19824916822add6ab09510a95a2a7e3d4e0 | |
parent | eb4a14fd0fa3d4e37dd9ad7892cac13c14bd1bbb (diff) | |
download | pyserial-git-7fc7da0d5a52eb4b3c0d5b9abafafb14dbd1281e.tar.gz |
leading zeros
-rw-r--r-- | pyserial/examples/test.py | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/pyserial/examples/test.py b/pyserial/examples/test.py index 0c71fd0..9b49df1 100644 --- a/pyserial/examples/test.py +++ b/pyserial/examples/test.py @@ -103,6 +103,7 @@ class SendEvent(threading.Thread): time.sleep(self.delay) if not self.stopped: self.serial.write(data("E")) + self.serial.flush() self.x.set() def isSet(self): @@ -167,19 +168,19 @@ class Test0_DataWires(unittest.TestCase): def test1_RTS(self): """Test RTS/CTS""" self.s.setRTS(0) - time.sleep(01.1) + time.sleep(1.1) self.failUnless(not self.s.getCTS(), "CTS -> 0") self.s.setRTS(1) - time.sleep(01.1) + time.sleep(1.1) self.failUnless(self.s.getCTS(), "CTS -> 1") def test2_DTR(self): """Test DTR/DSR""" self.s.setDTR(0) - time.sleep(01.1) + time.sleep(1.1) self.failUnless(not self.s.getDSR(), "DSR -> 0") self.s.setDTR(1) - time.sleep(01.1) + time.sleep(1.1) self.failUnless(self.s.getDSR(), "DSR -> 1") def test3_RI(self): |