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authorcliechti <cliechti@f19166aa-fa4f-0410-85c2-fa1106f25c8a>2002-07-31 00:53:06 +0000
committercliechti <cliechti@f19166aa-fa4f-0410-85c2-fa1106f25c8a>2002-07-31 00:53:06 +0000
commit619e45617e3cc767f864522802bcd9e37d0130f8 (patch)
tree377cb12acd394f365475461de8fed08a9ad5a96f /pyparallel/parallel/parallelwin32.py
parente5fa3b60238db8bfe839d8bbffc4a638719f6e95 (diff)
downloadpyserial-git-619e45617e3cc767f864522802bcd9e37d0130f8.tar.gz
added linux/ppdev implementation from Michael Ashton
synchronized method and class names between win and ppdev impl.
Diffstat (limited to 'pyparallel/parallel/parallelwin32.py')
-rw-r--r--pyparallel/parallel/parallelwin32.py38
1 files changed, 19 insertions, 19 deletions
diff --git a/pyparallel/parallel/parallelwin32.py b/pyparallel/parallel/parallelwin32.py
index 7c10c3f..21e8887 100644
--- a/pyparallel/parallel/parallelwin32.py
+++ b/pyparallel/parallel/parallelwin32.py
@@ -40,7 +40,7 @@
# 7 6 5 4 3 2 1 0
# . . . . . . . * Strobe ....... (pin 1), 1=low, 0=high (inverted)
# . . . . . . * . Auto Feed .... (pin 14), 1=low, 0=high (inverted)
-# . . . . . * . . Initialize ... (pin 16), 1=high, 0=low (true)
+# . . . . . * . . Initialize ... (pin 16), 1=high,0=low (true)
# . . . . * . . . Select ....... (pin 17), 1=low, 0=high (inverted)
# * * * * . . . . Unused
@@ -56,7 +56,7 @@ class Parallel:
def __init__(self, port = LPT1):
if port == LPT1:
self.dataRegAdr = LPT1_base
- elif port == LPT1:
+ elif port == LPT2:
self.dataRegAdr = LPT2_base
else:
raise ValueError("No such port available - expecting a number")
@@ -67,36 +67,36 @@ class Parallel:
_pyparallel.outp(self.dataRegAdr, value)
# control register output functions
- def setDataStrobe(self, state):
+ def setDataStrobe(self, level):
"""data strobe bit"""
- if state == 0:
- self.ctrlReg = self.ctrlReg | 0x01
- else:
+ if level:
self.ctrlReg = self.ctrlReg & ~0x01
+ else:
+ self.ctrlReg = self.ctrlReg | 0x01
_pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
- def setAutoFeed(self, state):
+ def setAutoFeed(self, level):
"""auto feed bit"""
- if state == 0:
- self.ctrlReg = self.ctrlReg | 0x02
- else:
+ if level:
self.ctrlReg = self.ctrlReg & ~0x02
+ else:
+ self.ctrlReg = self.ctrlReg | 0x02
_pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
- def setInitOut(self, state):
+ def setInitOut(self, level):
"""initialize bit"""
- if state == 0:
- self.ctrlReg = self.ctrlReg & ~0x04
- else:
+ if level:
self.ctrlReg = self.ctrlReg | 0x04
+ else:
+ self.ctrlReg = self.ctrlReg & ~0x04
_pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
- def setSelect(self, state):
+ def setSelect(self, level):
"""select bit"""
- if state == 0:
- self.ctrlReg = self.ctrlReg | 0x08
- else:
+ if level:
self.ctrlReg = self.ctrlReg & ~0x08
+ else:
+ self.ctrlReg = self.ctrlReg | 0x08
_pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
def getInError(self):
@@ -117,6 +117,6 @@ class Parallel:
def getInBusy(self):
"""input from busy pin"""
- return _pyparallel.inp(self.statusRegAdr)& 0x80 and 1
+ return not (_pyparallel.inp(self.statusRegAdr) & 0x80)