From a641aec03c07e3ec8a56401a8ee6b4052d6343b8 Mon Sep 17 00:00:00 2001 From: cliechti Date: Wed, 22 Jul 2009 00:24:41 +0000 Subject: implement patch from DanielC --- pyparallel/CHANGES.txt | 5 ++++- pyparallel/parallel/parallelwin32.py | 10 +++++++++- 2 files changed, 13 insertions(+), 2 deletions(-) (limited to 'pyparallel') diff --git a/pyparallel/CHANGES.txt b/pyparallel/CHANGES.txt index 94b0269..beef1e2 100644 --- a/pyparallel/CHANGES.txt +++ b/pyparallel/CHANGES.txt @@ -2,4 +2,7 @@ Version 0.1 29 Jul 2002 added to CVS Version 0.2 27 Jan 2005 - Windows version now using ctypes \ No newline at end of file + Windows version now using ctypes + +Version ... ... + added setDataDir to Windows backend diff --git a/pyparallel/parallel/parallelwin32.py b/pyparallel/parallel/parallelwin32.py index 5754578..c8f0d23 100644 --- a/pyparallel/parallel/parallelwin32.py +++ b/pyparallel/parallel/parallelwin32.py @@ -77,6 +77,14 @@ class Parallel: def setData(self, value): _pyparallel.outp(self.dataRegAdr, value) + def setDataDir( self, level): + """set for port as input, clear for output""" + if level: + self.ctrlReg |= 0x20 + else: + self.ctrlReg &= ~0x20 + _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg) + # control register output functions def setDataStrobe(self, level): """data strobe bit""" @@ -101,7 +109,7 @@ class Parallel: else: self.ctrlReg = self.ctrlReg & ~0x04 _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg) - + def setSelect(self, level): """select bit""" if level: -- cgit v1.2.1