class BitaccessMeta(type): """meta class that adds bit access properties to a parallel port implementation""" def __new__(self, classname, bases, classdict): klass = type.__new__(self, classname, bases, classdict) # status lines klass.paperOut = property(klass.getInPaperOut, None, "Read the PaperOut signal") # control lines klass.dataStrobe = property(None, klass.setDataStrobe, "Set the DataStrobe signal") # XXX ... other bits # data bits for bit in range(8): mask = (1<> shift) & mask def setter(self, b, shift=shift, mask=mask): self.setData((self.getData() & ~(mask<>4) & 0xf), (x & 0xf))) # test setting p._data = 0 (p.D4_D7, p.D0_D3) = (((x>>4) & 0xf), (x & 0xf)) self.failUnlessEqual(p._data, x) def testStatusbits(self): """bit by bit status lines""" # read the property: self.p._dummy = 0 self.failUnlessEqual(self.p.paperOut, 0) self.p._dummy = 1 self.failUnlessEqual(self.p.paperOut, 1) # read only, must not be writable: self.failUnlessRaises(AttributeError, setattr, self.p, 'paperOut', 1) def testControlbits(self): """bit by bit control lines""" self.p.dataStrobe = 0 self.failUnlessEqual(self.p._last, ('setDataStrobe', 0)) self.p.dataStrobe = 1 self.failUnlessEqual(self.p._last, ('setDataStrobe', 1)) # write only, must not be writable: self.failUnlessRaises(AttributeError, getattr, self.p, 'dataStrobe') sys.argv.append('-v') # When this module is executed from the command-line, it runs all its tests unittest.main()