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| author | Allan Sandfeld Jensen <allan.jensen@digia.com> | 2014-10-28 10:04:13 +0100 |
|---|---|---|
| committer | Allan Sandfeld Jensen <allan.jensen@theqtcompany.com> | 2014-10-30 11:50:39 +0100 |
| commit | 7296068ce76be5e0c33fd70918688f7ffb24bc72 (patch) | |
| tree | c99035d9b1e7ba5fda22c9d6c8413eda2bca13c4 /Source/JavaScriptCore | |
| parent | 4ab0f495a26ae18cb7be7a4ddb4c411eba06b398 (diff) | |
| download | qtwebkit-7296068ce76be5e0c33fd70918688f7ffb24bc72.tar.gz | |
Do not use unaligned access when disabled
Use the GCC feature defines to check for support for ARMv6 style
unaligned access support. This fixes configurations where it was
disabled and the ARMv6-M processors where it is not supported.
Change-Id: I00c9bb19ba582b64ecb9eaa6da9887ba0df8fd3c
Reviewed-by: Julien Brianceau <jbriance@cisco.com>
Reviewed-by: Jocelyn Turcotte <jocelyn.turcotte@digia.com>
Diffstat (limited to 'Source/JavaScriptCore')
| -rw-r--r-- | Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp | 2 | ||||
| -rw-r--r-- | Source/JavaScriptCore/assembler/MacroAssemblerARM.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp b/Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp index 6fc08bcb3..ca0fa210a 100644 --- a/Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp +++ b/Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp @@ -74,7 +74,7 @@ static bool isVFPPresent() const bool MacroAssemblerARM::s_isVFPPresent = isVFPPresent(); -#if CPU(ARMV5_OR_LOWER) +#if !CPU(ARM_FEATURE_UNALIGNED) /* On ARMv5 and below, natural alignment is required. */ void MacroAssemblerARM::load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest) { diff --git a/Source/JavaScriptCore/assembler/MacroAssemblerARM.h b/Source/JavaScriptCore/assembler/MacroAssemblerARM.h index 9058514dc..d9093413f 100644 --- a/Source/JavaScriptCore/assembler/MacroAssemblerARM.h +++ b/Source/JavaScriptCore/assembler/MacroAssemblerARM.h @@ -393,7 +393,7 @@ public: m_assembler.baseIndexTransfer32(ARMAssembler::LoadUint32, dest, address.base, address.index, static_cast<int>(address.scale), address.offset); } -#if CPU(ARMV5_OR_LOWER) +#if !CPU(ARM_FEATURE_UNALIGNED) void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest); #else void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest) |