// MIR for `slice_index_range` after PreCodegen fn slice_index_range(_1: &[u32], _2: std::ops::Range) -> &[u32] { debug slice => _1; // in scope 0 at $DIR/slice_index.rs:+0:26: +0:31 debug index => _2; // in scope 0 at $DIR/slice_index.rs:+0:41: +0:46 let mut _0: &[u32]; // return place in scope 0 at $DIR/slice_index.rs:+0:65: +0:71 let _3: &[u32]; // in scope 0 at $DIR/slice_index.rs:+1:6: +1:18 scope 1 (inlined #[track_caller] core::slice::index::> for [u32]>::index) { // at $DIR/slice_index.rs:21:6: 21:18 debug self => _1; // in scope 1 at $SRC_DIR/core/src/slice/index.rs:LL:COL debug index => _2; // in scope 1 at $SRC_DIR/core/src/slice/index.rs:LL:COL let _4: &[u32]; // in scope 1 at $SRC_DIR/core/src/slice/index.rs:LL:COL } bb0: { StorageLive(_4); // scope 1 at $SRC_DIR/core/src/slice/index.rs:LL:COL _4 = as SliceIndex<[u32]>>::index(move _2, _1) -> bb1; // scope 1 at $SRC_DIR/core/src/slice/index.rs:LL:COL // mir::Constant // + span: $SRC_DIR/core/src/slice/index.rs:LL:COL // + literal: Const { ty: for<'a> fn(std::ops::Range, &'a [u32]) -> &'a as SliceIndex<[u32]>>::Output { as SliceIndex<[u32]>>::index}, val: Value() } } bb1: { _3 = _4; // scope 1 at $SRC_DIR/core/src/slice/index.rs:LL:COL StorageDead(_4); // scope 1 at $SRC_DIR/core/src/slice/index.rs:LL:COL _0 = _3; // scope 0 at $DIR/slice_index.rs:+1:5: +1:18 return; // scope 0 at $DIR/slice_index.rs:+2:2: +2:2 } }