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authorH. Peter Anvin <hpa@zytor.com>2007-11-01 18:25:10 -0700
committerH. Peter Anvin <hpa@zytor.com>2007-11-01 18:25:10 -0700
commit816346554f9f2ef552639f7b4fbf413ea5ba8363 (patch)
treee10bab1482810fb0228a815468f71c6db20c93ea
parent3ec5ae0b9d6c9a01c2bb10a567327e7f96c6b0d8 (diff)
downloadsyslinux-816346554f9f2ef552639f7b4fbf413ea5ba8363.tar.gz
Code cleanup: get rid of hard-coded descriptor numbers
Get rid of hard-coded descriptor numbers, and instead use symbolic names for the descriptors derived from the calculated offset in the GDT.
-rw-r--r--bcopy32.inc34
-rw-r--r--com32.inc12
2 files changed, 30 insertions, 16 deletions
diff --git a/bcopy32.inc b/bcopy32.inc
index 330f2be6..87190d8e 100644
--- a/bcopy32.inc
+++ b/bcopy32.inc
@@ -37,24 +37,38 @@ __bcopy_start:
; This is in the .text segment since it needs to be
; contiguous with the rest of the bcopy stuff
-bcopy_gdt: dw bcopy_gdt_size-1 ; Null descriptor - contains GDT
+; GDT descriptor entry
+%macro desc 1
+bcopy_gdt.%1:
+PM_%1 equ bcopy_gdt.%1-bcopy_gdt
+%endmacro
+
+bcopy_gdt:
+ dw bcopy_gdt_size-1 ; Null descriptor - contains GDT
dd bcopy_gdt ; pointer for LGDT instruction
dw 0
+
+ desc CS16
dd 0000ffffh ; 08h Code segment, use16, readable,
dd 00009b00h ; present, dpl 0, cover 64K
+ desc DS16_4G
dd 0000ffffh ; 10h Data segment, use16, read/write,
dd 008f9300h ; present, dpl 0, cover all 4G
+ desc DS16_RM
dd 0000ffffh ; 18h Data segment, use16, read/write,
dd 00009300h ; present, dpl 0, cover 64K
; The next two segments are used for COM32 only
+ desc CS32
dd 0000ffffh ; 20h Code segment, use32, readable,
dd 00cf9b00h ; present, dpl 0, cover all 4G
+ desc DS32
dd 0000ffffh ; 28h Data segment, use32, read/write,
dd 00cf9300h ; present, dpl 0, cover all 4G
+
; TSS segment to keep Intel VT happy. Intel VT is
; unhappy about anything that doesn't smell like a
; full-blown 32-bit OS.
-.tss:
+ desc TSS
dw 104-1, DummyTSS ; 30h 32-bit task state segment
dd 00008900h ; present, dpl 0, 104 bytes @DummyTSS
bcopy_gdt_size: equ $-bcopy_gdt
@@ -88,7 +102,7 @@ bcopy: push eax
cli
call enable_a20
- mov byte [bcopy_gdt.tss+5],89h ; Mark TSS unbusy
+ mov byte [bcopy_gdt.TSS+5],89h ; Mark TSS unbusy
mov bx,ss ; Save the stack segment value!
@@ -96,9 +110,9 @@ bcopy: push eax
mov eax,cr0
or al,1
mov cr0,eax ; Enter protected mode
- jmp 08h:.in_pm
+ jmp PM_CS16:.in_pm
-.in_pm: mov ax,10h ; Data segment selector
+.in_pm: mov ax,PM_DS16_4G ; Data segment selector
mov es,ax
mov ds,ax
@@ -108,12 +122,12 @@ bcopy: push eax
; ss is NOT zero in general, so we have to preserve
; the value.
- mov al,18h ; Real-mode-like segment
+ mov al,PM_DS16_RM ; Real-mode-like segment
mov fs,ax
mov gs,ax
mov ss,ax
- mov al,30h ; Intel VT really doesn't want
+ mov al,PM_TSS ; Intel VT really doesn't want
ltr ax ; an invalid TR and LDTR, so give
xor ax,ax ; it something that it can use...
lldt ax ; (sigh)
@@ -166,7 +180,7 @@ bcopy: push eax
; jmp .exit
.exit:
- mov ax,18h ; "Real-mode-like" data segment
+ mov ax,PM_DS16_RM ; "Real-mode-like" data segment
mov es,ax
mov ds,ax
@@ -518,13 +532,13 @@ trampoline_to_pm:
mov eax,cr0
or al,1
mov cr0,eax ; Enter protected mode
- mov ax,28h ; 32-bit data segment selector
+ mov ax,PM_DS32 ; 32-bit data segment selector
mov es,ax
mov ds,ax
mov ss,ax
mov fs,ax
mov gs,ax
- jmp 020h:TrampolineBuf ; 20h = 32-bit code segment
+ jmp PM_CS32:TrampolineBuf
align 2
A20List dw a20_dunno, a20_none, a20_bios, a20_kbc, a20_fast
diff --git a/com32.inc b/com32.inc
index 8220c134..c4a1faa2 100644
--- a/com32.inc
+++ b/com32.inc
@@ -82,14 +82,14 @@ com32_enter_pm:
call enable_a20
.a20ok:
- mov byte [bcopy_gdt.tss+5],89h ; Mark TSS unbusy
+ mov byte [bcopy_gdt.TSS+5],89h ; Mark TSS unbusy
lgdt [bcopy_gdt] ; We can use the same GDT just fine
lidt [com32_pmidt] ; Set up the IDT
mov eax,cr0
or al,1
mov cr0,eax ; Enter protected mode
- jmp 20h:.in_pm
+ jmp PM_CS32:.in_pm
bits 32
.in_pm:
@@ -98,12 +98,12 @@ com32_enter_pm:
mov gs,eax
lldt ax
- mov al,28h ; Set up data segments
+ mov al,PM_DS32 ; Set up data segments
mov es,eax
mov ds,eax
mov ss,eax
- mov al,30h ; Be nice to Intel's VT by
+ mov al,PM_TSS ; Be nice to Intel's VT by
ltr ax ; giving it a valid TR
mov esp,[PMESP] ; Load protmode %esp if available
@@ -182,11 +182,11 @@ com32_enter_rm:
cld
mov [PMESP],esp ; Save exit %esp
xor esp,esp ; Make sure the high bits are zero
- jmp 08h:.in_pm16 ; Return to 16-bit mode first
+ jmp PM_CS16:.in_pm16 ; Return to 16-bit mode first
bits 16
.in_pm16:
- mov ax,18h ; Real-mode-like segment
+ mov ax,PM_DS16_RM ; Real-mode-like segment
mov es,ax
mov ds,ax
mov ss,ax