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author | Alexey Brodkin <abrodkin@synopsys.com> | 2017-05-19 16:55:24 +0200 |
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committer | Zbigniew Jędrzejewski-Szmek <zbyszek@in.waw.pl> | 2017-05-19 10:55:24 -0400 |
commit | 27b09f1f1ed29edb9c52ad8414c2344974a07a23 (patch) | |
tree | 442a6e52577778b902e682c8e7be295a4a476dac /src/basic/architecture.c | |
parent | 4e6b9b2049188bca6d413818856ac130dd773097 (diff) | |
download | systemd-27b09f1f1ed29edb9c52ad8414c2344974a07a23.tar.gz |
architecture: add Synopsys DesignWare ARC cores support (#5992)
DesignWare ARC Processors are a family of 32-bit CPUs from Synopsys
used extensively in SoCs of different vendors.
Diffstat (limited to 'src/basic/architecture.c')
-rw-r--r-- | src/basic/architecture.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/basic/architecture.c b/src/basic/architecture.c index 5a3dc08a4a..2518dd8112 100644 --- a/src/basic/architecture.c +++ b/src/basic/architecture.c @@ -132,6 +132,9 @@ int uname_architecture(void) { # elif __SIZEOF_POINTER__ == 8 { "riscv", ARCHITECTURE_RISCV64 }, # endif +#elif defined(__arc__) + { "arc", ARCHITECTURE_ARC }, + { "arceb", ARCHITECTURE_ARC_BE }, #else #error "Please register your architecture here!" #endif @@ -185,6 +188,8 @@ static const char *const architecture_table[_ARCHITECTURE_MAX] = { [ARCHITECTURE_NIOS2] = "nios2", [ARCHITECTURE_RISCV32] = "riscv32", [ARCHITECTURE_RISCV64] = "riscv64", + [ARCHITECTURE_ARC] = "arc", + [ARCHITECTURE_ARC_BE] = "arc-be", }; DEFINE_STRING_TABLE_LOOKUP(architecture, int); |