ODROID-GOU:Introduce new board 'ODROID-GOU'. odroid-go ultra

Signed-off-by: ckkim <changkon12@gmail.com>
Change-Id: Ib03ffba8ed20ab839a82c4d490c26a20c244ad04

25 files changed, 2190 insertions, 6 deletions

diff --git a/arch/arm/include/asm/arch-g12b/i2c.h b/arch/arm/include/asm/arch-g12b/i2c.h
index b33594a3a9..61652931b3 100644
--- a/arch/arm/include/asm/arch-g12b/i2c.h
+++ b/arch/arm/include/asm/arch-g12b/i2c.h
@@ -173,12 +173,16 @@ struct i2c_msg {
 
 /*i2c master AO*/
 
-
 #define MESON_I2C_MASTER_AO_GPIOAO_4_REG	(P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */
 #define MESON_I2C_MASTER_AO_GPIOAO_4_BIT	(1<<8)
 #define MESON_I2C_MASTER_AO_GPIOAO_5_REG	(P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */
 #define MESON_I2C_MASTER_AO_GPIOAO_5_BIT	(1<<9)
 
+#define MESON_I2C_MASTER_AO_GPIOAO_2_REG	(P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */
+#define MESON_I2C_MASTER_AO_GPIOAO_2_BIT	(1<<8)
+#define MESON_I2C_MASTER_AO_GPIOAO_3_REG	(P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */
+#define MESON_I2C_MASTER_AO_GPIOAO_3_BIT	(1<<12)
+
 /*i2c slave*/
 #define MESON_I2C_SLAVE_JTAG_TMS_REG			CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
 #define MESON_I2C_SLAVE_JTAG_TMS_BIT			(1<<13)
diff --git a/board/amlogic/Kconfig b/board/amlogic/Kconfig
index 3578dbabf6..64a4db5360 100644
--- a/board/amlogic/Kconfig
+++ b/board/amlogic/Kconfig
@@ -284,6 +284,11 @@ config ODROID_GO4
 	select ODROID_COMMON
 	default n
 
+config ODROID_GOU
+	bool "Support Hardkernel ODROID-GO Ultra"
+	select ODROID_COMMON
+	default n
+
 if GXB_SKT_V1
 source "board/amlogic/gxb_skt_v1/Kconfig"
 endif
@@ -552,3 +557,7 @@ endif
 if ODROID_GO4
 source "board/hardkernel/odroidgo4/Kconfig"
 endif
+
+if ODROID_GOU
+source "board/hardkernel/odroidgou/Kconfig"
+endif
diff --git a/board/hardkernel/odroid-common/board.c b/board/hardkernel/odroid-common/board.c
index 2a72cc62dd..b0c3e67220 100755
--- a/board/hardkernel/odroid-common/board.c
+++ b/board/hardkernel/odroid-common/board.c
@@ -87,6 +87,11 @@ static unsigned int get_hw_revision(void)
 		hwrev = BOARD_REVISION(2020, 12, 11);
 	else 
 		hwrev = BOARD_REVISION(2020, 10, 6);
+#elif defined(CONFIG_ODROID_GOU)
+	if (IS_RANGE(adc, 80, 100))	/* avg : 90 */
+		hwrev = BOARD_REVISION(2021, 7, 6);
+	else
+		hwrev = BOARD_REVISION(2020, 10, 6);
 #endif
 
 	printf("ADC=%d, hwrev=0x%x\n", adc, hwrev);
@@ -133,4 +138,9 @@ int board_is_odroidgo4(void)
 {
 	return (board_revision() >= 0x20201006);
 }
+#elif defined(CONFIG_ODROID_GOU)
+int board_is_odroidgou(void)
+{
+	return (board_revision() >= 0x20201006);
+}
 #endif
diff --git a/board/hardkernel/odroid-common/odroid-common.h b/board/hardkernel/odroid-common/odroid-common.h
index 8c47525e9a..61156c3a95 100644
--- a/board/hardkernel/odroid-common/odroid-common.h
+++ b/board/hardkernel/odroid-common/odroid-common.h
@@ -37,6 +37,8 @@ int board_is_odroidc4(void);
 int board_is_odroidhc4(void);
 #elif defined(CONFIG_ODROID_GO4)
 int board_is_odroidgo4(void);
+#elif defined(CONFIG_ODROID_GOU)
+int board_is_odroidgou(void);
 #endif
 
 /*
diff --git a/board/hardkernel/odroidgou/Kconfig b/board/hardkernel/odroidgou/Kconfig
new file mode 100755
index 0000000000..b8b7bd65ff
--- /dev/null
+++ b/board/hardkernel/odroidgou/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_G12B
+
+config SYS_CPU
+	string
+	default "armv8"
+
+config SYS_BOARD
+	string
+	default "odroidgou"
+
+config SYS_VENDOR
+	string
+	default "hardkernel"
+
+config SYS_SOC
+	string
+	default "g12b"
+
+config SYS_CONFIG_NAME
+	default "odroidgou"
+
+endif
diff --git a/board/hardkernel/odroidgou/Makefile b/board/hardkernel/odroidgou/Makefile
new file mode 100755
index 0000000000..30353a42b3
--- /dev/null
+++ b/board/hardkernel/odroidgou/Makefile
@@ -0,0 +1,4 @@
+EXTRA_CFLAGS += -Iboard/hardkernel/odroid-common
+
+obj-y += $(BOARD).o
+obj-$(CONFIG_AML_LCD) += gou_lcd.o
\ No newline at end of file
diff --git a/board/hardkernel/odroidgou/aml-user-key.sig b/board/hardkernel/odroidgou/aml-user-key.sig
new file mode 100755
index 0000000000..2ceabc16e0
--- /dev/null
+++ b/board/hardkernel/odroidgou/aml-user-key.sig
diff --git a/board/hardkernel/odroidgou/firmware/scp_task/pwm_ctrl.h b/board/hardkernel/odroidgou/firmware/scp_task/pwm_ctrl.h
new file mode 100755
index 0000000000..2daf33a316
--- /dev/null
+++ b/board/hardkernel/odroidgou/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,50 @@
+/*
+ * board/amlogic/odroidn2/firmware/scp_task/pwm_ctrl.h
+ * table for Dynamic Voltage/Frequency Scaling
+ */
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table_ee[][2] = {
+	{ 0x100000,  693},
+	{ 0x0f0001,  703},
+	{ 0x0e0002,  713},
+	{ 0x0d0003,  723},
+	{ 0x0c0004,  733},
+	{ 0x0b0005,  743},
+	{ 0x0a0006,  753},
+	{ 0x090007,  763},
+	{ 0x080008,  773},
+	{ 0x070009,  783},
+	{ 0x06000a,  792},
+	{ 0x05000b,  802},
+	{ 0x04000c,  812},
+	{ 0x03000d,  822},
+	{ 0x02000e,  832},
+	{ 0x01000f,  842},
+	{ 0x000010,  852},
+	{ 0x0000c0,  862},
+};
+
+static int pwm_voltage_table_ee_new[][2] = {
+	{ 0x0f0001,  700},
+	{ 0x0e0002,  710},
+	{ 0x0d0003,  720},
+	{ 0x0c0004,  730},
+	{ 0x0b0005,  740},
+	{ 0x0a0006,  750},
+	{ 0x090007,  760},
+	{ 0x080008,  770},
+	{ 0x070009,  780},
+	{ 0x06000a,  790},
+	{ 0x05000b,  800},
+	{ 0x04000c,  810},
+	{ 0x03000d,  820},
+	{ 0x02000e,  830},
+	{ 0x01000f,  840},
+	{ 0x000010,  850},
+	{ 0x000040,  860},
+	{ 0x000160,  870},	/* 863 */
+};
+
+#endif //__PWM_CTRL_H__
diff --git a/board/hardkernel/odroidgou/firmware/scp_task/pwr_ctrl.c b/board/hardkernel/odroidgou/firmware/scp_task/pwr_ctrl.c
new file mode 100755
index 0000000000..a551e19546
--- /dev/null
+++ b/board/hardkernel/odroidgou/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,265 @@
+/*
+ * board/amlogic/odroidn2/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+*/
+
+#include <gpio.h>
+#include "pwm_ctrl.h"
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#ifdef CONFIG_GPIO_WAKEUP
+#include <gpio_key.h>
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+unsigned int enable_wol = 0;   /* disable Wake-On-Lan by default*/
+unsigned int enable_5V_system_power = 0;	/* disable 5V system power (USB) by default*/
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+	unsigned int to, pwm_size = 0;
+	static int (*pwm_voltage_ee)[2];
+
+	/* BOOT_9 = H use PWM_CFG0(0.67v-0.97v), =L use PWM_CFG1(0.69v-0.89v) */
+	/*set BOOT_9 input mode*/
+	writel((readl(PREG_PAD_GPIO0_EN_N) | 0x200), PREG_PAD_GPIO0_EN_N);
+	if (((readl(PREG_PAD_GPIO0_EN_N) & 0x200 ) == 0x200) &&
+			((readl(PREG_PAD_GPIO0_I) & 0x200 ) == 0x0)) {
+		uart_puts("use vddee new table!");
+		uart_puts("\n");
+		pwm_voltage_ee = pwm_voltage_table_ee_new;
+		pwm_size = ARRAY_SIZE(pwm_voltage_table_ee_new);
+	} else {
+		uart_puts("use vddee table!");
+		uart_puts("\n");
+		pwm_voltage_ee = pwm_voltage_table_ee;
+		pwm_size = ARRAY_SIZE(pwm_voltage_table_ee);
+	}
+
+	for (to = 0; to < pwm_size; to++) {
+		if (pwm_voltage_ee[to][1] >= target_voltage) {
+			break;
+		}
+	}
+
+	if (to >= pwm_size) {
+		to = pwm_size - 1;
+	}
+
+	writel(*(*(pwm_voltage_ee + to)), AO_PWM_PWM_B);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+	if (!enable_5V_system_power)
+	{
+		/*set gpioH_8 low to power off vcc 5v*/
+		writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
+		writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+	}
+
+	/*set gpioao_4 low to power off vcck_a*/
+	writel(readl(AO_GPIO_O) & (~(1 << 4)), AO_GPIO_O);
+	writel(readl(AO_GPIO_O_EN_N) & (~(1 << 4)), AO_GPIO_O_EN_N);
+	writel(readl(AO_RTI_PIN_MUX_REG) & (~(0xf << 16)), AO_RTI_PIN_MUX_REG);
+
+	if (!enable_5V_system_power && !enable_wol) {
+		/*set test_n low to power off vcck_b & vcc 3.3v*/
+		writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
+		writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+		writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+	}
+
+	/*step down ee voltage*/
+	set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+	/*step up ee voltage*/
+	set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+	if (!enable_5V_system_power && !enable_wol) {
+		/*set test_n high to power on vcck_b & vcc 3.3v*/
+		writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
+		writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+		writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+		_udelay(100);
+	}
+
+	/*set gpioao_4 high to power on vcck_a*/
+	writel(readl(AO_GPIO_O) | (1 << 4), AO_GPIO_O);
+	writel(readl(AO_GPIO_O_EN_N) & (~(1 << 4)), AO_GPIO_O_EN_N);
+	writel(readl(AO_RTI_PIN_MUX_REG) & (~(0xf << 16)), AO_RTI_PIN_MUX_REG);
+	_udelay(100);
+
+	if (!enable_5V_system_power)
+	{
+		/*set gpioH_8 high to power on vcc 5v*/
+		writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
+		writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+	}
+	_udelay(10000);
+
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+	struct wakeup_info *p = (struct wakeup_info *)response;
+	struct wakeup_gpio_info *gpio;
+	unsigned val;
+	unsigned i = 0;
+
+	p->status = RESPONSE_OK;
+	val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+			RTC_WAKEUP_SRC | BT_WAKEUP_SRC | ETH_PHY_GPIO_SRC);
+
+#ifdef CONFIG_CEC_WAKEUP
+	val |= CECB_WAKEUP_SRC;
+#endif
+
+	p->sources = val;
+
+	/* Power Key: AO_GPIO[3]*/
+	gpio = &(p->gpio_info[i]);
+	gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+	gpio->gpio_in_idx = GPIOAO_3;
+	gpio->gpio_in_ao = 1;
+	gpio->gpio_out_idx = -1;
+	gpio->gpio_out_ao = -1;
+	gpio->irq = IRQ_AO_GPIO0_NUM;
+	gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+	p->gpio_info_count = ++i;
+
+	/* External RTC: AO_GPIO[7]*/
+	gpio = &(p->gpio_info[i]);
+	gpio->wakeup_id = RTC_WAKEUP_SRC;
+	gpio->gpio_in_idx = GPIOAO_7;
+	gpio->gpio_in_ao = 1;
+	gpio->gpio_out_idx = -1;
+	gpio->gpio_out_ao = -1;
+	gpio->irq = IRQ_AO_GPIO0_NUM;
+	gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+	p->gpio_info_count = ++i;
+
+	if (enable_wol) {
+		/* Ethernet: GPIOZ_14 */
+		gpio = &(p->gpio_info[i]);
+		gpio->wakeup_id = ETH_PHY_GPIO_SRC;
+		gpio->gpio_in_idx = GPIOZ_14;
+		gpio->gpio_in_ao = 0;
+		gpio->gpio_out_idx = -1;
+		gpio->gpio_out_ao = -1;
+		gpio->irq = IRQ_GPIO1_NUM;
+		gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+		p->gpio_info_count = ++i;
+	}
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+	int exit_reason = 0;
+	unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+#ifdef CONFIG_GPIO_WAKEUP
+	unsigned int is_gpiokey = 0;
+#endif
+
+	backup_remote_register();
+	init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+		if (hdmi_cec_func_config & 0x1) {
+			remote_cec_hw_reset();
+			cec_node_init();
+		}
+#endif
+
+#ifdef CONFIG_GPIO_WAKEUP
+	is_gpiokey = init_gpio_key();
+#endif
+
+	do {
+		#ifdef CONFIG_CEC_WAKEUP
+		if (!cec_msg.log_addr)
+			cec_node_init();
+		else {
+			if (readl(AO_CECB_INTR_STAT) & CECB_IRQ_RX_EOM) {
+				if (cec_power_on_check())
+					exit_reason = CEC_WAKEUP;
+			}
+		}
+		#endif
+		if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+			irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+			if (remote_detect_key())
+				exit_reason = REMOTE_WAKEUP;
+		}
+
+		if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
+			irq[IRQ_VRTC] = 0xFFFFFFFF;
+			exit_reason = RTC_WAKEUP;
+		}
+
+		if (enable_wol && (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM)) {
+			irq[IRQ_GPIO1] = 0xFFFFFFFF;
+			if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 14))
+					&& (readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 14)))
+				exit_reason = ETH_PHY_GPIO;
+		}
+
+		if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+			unsigned val = readl(AO_GPIO_I);
+
+			irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+			if ((val & (1 << 3)) == 0)
+				exit_reason = POWER_KEY_WAKEUP;
+			else if ((val & (1 << 7)) == 0)
+				exit_reason = RTC_WAKEUP;
+		}
+
+		if (irq[IRQ_ETH_PTM] == IRQ_ETH_PMT_NUM) {
+			irq[IRQ_ETH_PTM]= 0xFFFFFFFF;
+			exit_reason = ETH_PMT_WAKEUP;
+		}
+
+#ifdef CONFIG_GPIO_WAKEUP
+		if (is_gpiokey) {
+			if (gpio_detect_key())
+				exit_reason = GPIO_WAKEUP;
+		}
+#endif
+		if (exit_reason)
+			break;
+		else
+			__switch_idle_task();
+	} while (1);
+
+	restore_remote_register();
+
+	return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+	pwr_op->power_off_at_24M = power_off_at_24M;
+	pwr_op->power_on_at_24M = power_on_at_24M;
+	pwr_op->detect_key = detect_key;
+	pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/hardkernel/odroidgou/firmware/timing.c b/board/hardkernel/odroidgou/firmware/timing.c
new file mode 100755
index 0000000000..6703b10278
--- /dev/null
+++ b/board/hardkernel/odroidgou/firmware/timing.c
@@ -0,0 +1,428 @@
+/*
+ * board/hardkernel/odroidn2/firmware/timing.c
+ *
+ * (C) Copyright 2018 Hardkernel Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+*/
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ *            #define CONFIG_DDR_CHL_AUTO					0xF
+ *            #define CONFIG_DDR0_16BIT_CH0				0x1
+ *            #define CONFIG_DDR0_16BIT_RANK01_CH0		0x4
+ *            #define CONFIG_DDR0_32BIT_RANK0_CH0			0x2
+ *            #define CONFIG_DDR0_32BIT_RANK01_CH01		0x3
+ *            #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0	0x5
+ *            #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0	0x6
+ * DramType:
+ *            #define CONFIG_DDR_TYPE_DDR3				0
+ *            #define CONFIG_DDR_TYPE_DDR4				1
+ *            #define CONFIG_DDR_TYPE_LPDDR4				2
+ *            #define CONFIG_DDR_TYPE_LPDDR3				3
+ * DRAMFreq:
+ *            {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1				0
+#define DDR_RFC_TYPE_DDR3_512Mbx2				1
+#define DDR_RFC_TYPE_DDR3_512Mbx4				2
+#define DDR_RFC_TYPE_DDR3_512Mbx8				3
+#define DDR_RFC_TYPE_DDR3_512Mbx16				4
+#define DDR_RFC_TYPE_DDR4_2Gbx1					5
+#define DDR_RFC_TYPE_DDR4_2Gbx2					6
+#define DDR_RFC_TYPE_DDR4_2Gbx4					7
+#define DDR_RFC_TYPE_DDR4_2Gbx8					8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1				9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1				10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1				11
+
+#define CONFIG_DDR4_DEFAULT_CLK		1320
+
+ddr_set_t __ddr_setting[] = {
+{
+	/* lpddr4 */
+	.board_id			= CONFIG_BOARD_ID_MASK,
+	.version			= 1,
+	//.dram_rank_config		= CONFIG_DDR0_32BIT_RANK01_CH0,
+	.dram_rank_config		= CONFIG_DDR0_32BIT_RANK01_CH01,
+	.ddr_rfc_type			= DDR_RFC_TYPE_LPDDR4_8Gbx1,
+	.DramType			= CONFIG_DDR_TYPE_LPDDR4,
+	.DRAMFreq			= {1392, 0, 0, 0},
+	.ddr_base_addr			= CFG_DDR_BASE_ADDR,
+	.ddr_start_offset		= CFG_DDR_START_OFFSET,
+	.imem_load_addr			= 0xFFFC0000, //sram
+	.dmem_load_size			= 0x1000, //4K
+
+	.DisabledDbyte			= 0xf0,
+	.Is2Ttiming			= 0,
+	.HdtCtrl			= 0xa,
+	.dram_cs0_size_MB		= 0xffff,//1024,
+	.dram_cs1_size_MB		= 0xffff,//1024,
+	.training_SequenceCtrl		= {0x131f,0x61}, //ddr3 0x21f 0x31f
+	.phy_odt_config_rank		= {0x23,0x13}, //use 0x23 0x13  compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+	.dfi_odt_config			= 0x0d0d,  //use 0d0d compatibility with 1rank and 2rank  //0808
+	.PllBypassEn			= 0, //bit0-ps0,bit1-ps1
+	.ddr_rdbi_wr_enable		= 0,
+	.clk_drv_ohm			= 40,
+	.cs_drv_ohm			= 40,
+	.ac_drv_ohm			= 40,
+	.soc_data_drv_ohm_p		= 40,
+	.soc_data_drv_ohm_n		= 40,
+	.soc_data_odt_ohm_p		= 0,
+	.soc_data_odt_ohm_n		= 120,
+	.dram_data_drv_ohm		= 40, //lpddr4 sdram only240/1-6
+	.dram_data_odt_ohm		= 120,
+	.dram_ac_odt_ohm		= 120,
+	.lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq     0 2/5 vddq
+	.soc_clk_slew_rate		= 0x3ff,//0x253,
+	.soc_cs_slew_rate		= 0x100,//0x253,
+	.soc_ac_slew_rate		= 0x100,//0x253,
+	.soc_data_slew_rate		= 0x1ff,
+	.vref_output_permil		= 350,//200,
+	.vref_receiver_permil		= 0,
+	.vref_dram_permil		= 0,
+	//.vref_reverse			= 0,
+	.ac_trace_delay			= {00,0x0,0,0,0,0,0x0,00},
+	//.ac_trace_delay		= {32,32,32,32,32,32,32,32,32,32},
+	.ac_pinmux				= {00,00},
+	.ddr_dmc_remap			= {
+							[0] = ( 5 |  6 << 5 |  7 << 10 |  8<< 15 | 9<< 20 | 10 << 25 ),
+							[1] = ( 11|  0 << 5 |  0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+							[2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+							[3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+							[4] = ( 30| 12 << 5 | 13 << 10 |  14<< 15 |  0 << 20 |  0 << 25 ),
+	},
+	.ddr_lpddr34_ca_remap	= {00,00},
+	.ddr_lpddr34_dq_remap	= {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29},
+	.dram_rtt_nom_wr_park	= {00,00},
+
+	/* pll ssc config:
+	 *
+	 *   pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+	 *      ppm = strength * 500
+	 *      mode: 0=center, 1=up, 2=down
+	 *
+	 *   eg:
+	 *     1. config 1000ppm center ss. then mode=0, strength=2
+	 *        .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+	 *     2. config 3000ppm down ss. then mode=2, strength=6
+	 *        .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+	 */
+	.pll_ssc_mode			= (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+	.ddr_func				= DDR_FUNC,
+	.magic					= DRAM_CFG_MAGIC,
+	.diagnose				= CONFIG_DIAGNOSE_DISABLE,
+	.bitTimeControl_2d      = 1,
+	.fast_boot[0]			= 1,
+},
+
+#if 0
+{
+	/* odroid-n2 ddr4 : (4Gbitx2)x2, (8Gbitx2)x2 */
+	.board_id			= CONFIG_BOARD_ID_MASK,
+	.version			= 1,
+	.dram_rank_config		= CONFIG_DDR0_32BIT_RANK01_CH0, /* bus width 32bit, use cs0 cs1 */
+	.DramType			= CONFIG_DDR_TYPE_DDR4,
+	/* 912 (DDR4-1866) / 1056 (DDR4-2133) / 1200 (DDR4-2400)/ 1320 (DDR4-2666) */
+	.DRAMFreq			= {CONFIG_DDR4_DEFAULT_CLK, 0, 0, 0},
+	.ddr_rfc_type			= DDR_RFC_TYPE_DDR4_2Gbx8,
+	.ddr_base_addr			= CFG_DDR_BASE_ADDR,
+	.ddr_start_offset		= CFG_DDR_START_OFFSET,
+	.imem_load_addr			= 0xFFFC0000,
+	.dmem_load_size			= 0x1000,
+
+	.DisabledDbyte			= 0xf0,
+	.Is2Ttiming			= 1,
+	.HdtCtrl			= 0xC8,
+	.dram_cs0_size_MB		= 0xffff,
+	.dram_cs1_size_MB		= 0xffff,
+	.training_SequenceCtrl		= {0x31f,0x61},
+	.phy_odt_config_rank		= {0x23,0x13},
+	.dfi_odt_config			= 0x0808,
+	.PllBypassEn			= 0,
+	.ddr_rdbi_wr_enable		= 0,
+	.clk_drv_ohm			= 40,
+	.cs_drv_ohm			= 40,
+	.ac_drv_ohm			= 40,
+	.soc_data_drv_ohm_p		= 34,
+	.soc_data_drv_ohm_n		= 34,
+	.soc_data_odt_ohm_p		= 60,
+	.soc_data_odt_ohm_n		= 0,
+	.dram_data_drv_ohm		= 48,
+	.dram_data_odt_ohm		= 60,
+	.dram_ac_odt_ohm		= 0,
+	.soc_clk_slew_rate		= 0x3ff,
+	.soc_cs_slew_rate		= 0x3ff,
+	.soc_ac_slew_rate		= 0x3ff,
+	.soc_data_slew_rate		= 0x2ff,
+	.vref_output_permil		= 500,
+	.vref_receiver_permil		= 700,
+	.vref_dram_permil		= 700,
+	//.vref_reverse			= 0,
+	.ac_trace_delay			= {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0},
+	.ac_pinmux			= {00, 00},
+	.ddr_dmc_remap			= {
+							[0] = ( 5 |  7 << 5 |  8 << 10 |  9 << 15 | 10 << 20 | 11 << 25 ),
+							[1] = ( 12|  0 << 5 |  0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+							[2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+							[3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+							[4] = ( 30| 13 << 5 | 20 << 10 |  6 << 15 |  0 << 20 |  0 << 25 ),
+	},
+	.ddr_lpddr34_ca_remap		= {00,00},
+	.ddr_lpddr34_dq_remap		= {00,00},
+	.dram_rtt_nom_wr_park		= {00,00},
+	.pll_ssc_mode			= 0,
+	.ddr_func			= DDR_FUNC,
+	.magic				= DRAM_CFG_MAGIC,
+},
+{
+	/* odroid-n2 ddr4 : 8Gbitx2 */
+	.board_id			= CONFIG_BOARD_ID_MASK,
+	.version			= 1,
+	.dram_rank_config		= CONFIG_DDR0_32BIT_RANK0_CH0, /* bus width 32bit, use cs0 only */
+	.DramType			= CONFIG_DDR_TYPE_DDR4,
+	/* 912 (DDR4-1866) / 1056 (DDR4-2133) / 1200 (DDR4-2400)/ 1320 (DDR4-2666) */
+	.DRAMFreq			= {CONFIG_DDR4_DEFAULT_CLK, 0, 0, 0},
+	.ddr_rfc_type			= DDR_RFC_TYPE_DDR4_2Gbx8,
+	.ddr_base_addr			= CFG_DDR_BASE_ADDR,
+	.ddr_start_offset		= CFG_DDR_START_OFFSET,
+	.imem_load_addr			= 0xFFFC0000,
+	.dmem_load_size			= 0x1000,
+
+	.DisabledDbyte			= 0xf0,
+	.Is2Ttiming			= 1,
+	.HdtCtrl			= 0xC8,
+	.dram_cs0_size_MB		= 0xffff,
+	.dram_cs1_size_MB		= 0,
+	.training_SequenceCtrl		= {0x31f,0x61},
+	.phy_odt_config_rank		= {0x23,0x13},
+	.dfi_odt_config			= 0x0808,
+	.PllBypassEn			= 0,
+	.ddr_rdbi_wr_enable		= 0,
+	.clk_drv_ohm			= 40,
+	.cs_drv_ohm			= 40,
+	.ac_drv_ohm			= 40,
+	.soc_data_drv_ohm_p		= 34,
+	.soc_data_drv_ohm_n		= 34,
+	.soc_data_odt_ohm_p		= 60,
+	.soc_data_odt_ohm_n		= 0,
+	.dram_data_drv_ohm		= 48,
+	.dram_data_odt_ohm		= 60,
+	.dram_ac_odt_ohm		= 0,
+	.soc_clk_slew_rate		= 0x3ff,
+	.soc_cs_slew_rate		= 0x3ff,
+	.soc_ac_slew_rate		= 0x3ff,
+	.soc_data_slew_rate		= 0x2ff,
+	.vref_output_permil		= 500,
+	.vref_receiver_permil		= 700,
+	.vref_dram_permil		= 700,
+	//.vref_reverse			= 0,
+	.ac_trace_delay			= {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0},
+	.ac_pinmux			= {00, 00},
+	.ddr_dmc_remap			= {
+							[0] = ( 5 |  7 << 5 |  8 << 10 |  9 << 15 | 10 << 20 | 11 << 25 ),
+							[1] = ( 12|  0 << 5 |  0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+							[2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+							[3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+							[4] = ( 30| 13 << 5 | 20 << 10 |  6 << 15 |  0 << 20 |  0 << 25 ),
+	},
+	.ddr_lpddr34_ca_remap		= {00,00},
+	.ddr_lpddr34_dq_remap		= {00,00},
+	.dram_rtt_nom_wr_park		= {00,00},
+	.pll_ssc_mode			= 0,
+	.ddr_func			= DDR_FUNC,
+	.magic				= DRAM_CFG_MAGIC,
+},
+#endif
+};
+
+pll_set_t __pll_setting = {
+	.cpu_clk				= CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+	.pxp					= 1,
+#else
+	.pxp					= 0,
+#endif
+	.spi_ctrl				= 0,
+	.lCustomerID			= CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+	.debug_mode				= CONFIG_DEBUG_MODE,
+	.ddr_clk_debug			= CONFIG_DDR_CLK_DEBUG,
+	.cpu_clk_debug			= CONFIG_CPU_CLK_DEBUG,
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+	/* demo, user defined override register */
+	{0xaabbccdd, 0, 0, 0, 0, 0},
+	{0x11223344, 0, 0, 0, 0, 0},
+	{0, 0, 0, 0, 0, 0},
+};
+
+#define VCCK_VAL				CONFIG_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL				CONFIG_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if   (VCCK_VAL == 800)
+	#define VCCK_VAL_REG	0x00150007
+#elif (VCCK_VAL == 810)
+	#define VCCK_VAL_REG	0x00140008
+#elif (VCCK_VAL == 820)
+	#define VCCK_VAL_REG	0x00130009
+#elif (VCCK_VAL == 830)
+	#define VCCK_VAL_REG	0x0012000a
+#elif (VCCK_VAL == 840)
+	#define VCCK_VAL_REG	0x0011000b
+#elif (VCCK_VAL == 850)
+	#define VCCK_VAL_REG	0x0010000c
+#elif (VCCK_VAL == 860)
+	#define VCCK_VAL_REG	0x000f000d
+#elif (VCCK_VAL == 870)
+	#define VCCK_VAL_REG	0x000e000e
+#elif (VCCK_VAL == 880)
+	#define VCCK_VAL_REG	0x000d000f
+#elif (VCCK_VAL == 890)
+	#define VCCK_VAL_REG	0x000c0010
+#elif (VCCK_VAL == 900)
+	#define VCCK_VAL_REG	0x000b0011
+#elif (VCCK_VAL == 910)
+	#define VCCK_VAL_REG	0x000a0012
+#elif (VCCK_VAL == 920)
+	#define VCCK_VAL_REG	0x00090013
+#elif (VCCK_VAL == 930)
+	#define VCCK_VAL_REG	0x00080014
+#elif (VCCK_VAL == 940)
+	#define VCCK_VAL_REG	0x00070015
+#elif (VCCK_VAL == 950)
+	#define VCCK_VAL_REG	0x00060016
+#elif (VCCK_VAL == 960)
+	#define VCCK_VAL_REG	0x00050017
+#elif (VCCK_VAL == 970)
+	#define VCCK_VAL_REG	0x00040018
+#elif (VCCK_VAL == 980)
+	#define VCCK_VAL_REG	0x00030019
+#elif (VCCK_VAL == 990)
+	#define VCCK_VAL_REG	0x0002001a
+#elif (VCCK_VAL == 1000)
+	#define VCCK_VAL_REG	0x0001001b
+#elif (VCCK_VAL == 1010)
+	#define VCCK_VAL_REG	0x0000001c
+#else
+	#error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG0: VDDEE PWM table  0.69v-0.862v*/
+/* VDDEE_VAL_REG1: VDDEE PWM table  0.69v-0.863v*/
+#if    (VDDEE_VAL == 800)
+	#define VDDEE_VAL_REG0	0x0005000b
+	#define VDDEE_VAL_REG1	0x0005000b
+#elif (VDDEE_VAL == 810)
+	#define VDDEE_VAL_REG0	0x0004000c
+	#define VDDEE_VAL_REG1	0x0004000c
+#elif (VDDEE_VAL == 820)
+	#define VDDEE_VAL_REG0	0x0003000d
+	#define VDDEE_VAL_REG1	0x0003000d
+#elif (VDDEE_VAL == 830)
+	#define VDDEE_VAL_REG0	0x0002000e
+	#define VDDEE_VAL_REG1	0x0002000e
+#elif (VDDEE_VAL == 840)
+	#define VDDEE_VAL_REG0	0x0001000f
+	#define VDDEE_VAL_REG1	0x0001000f
+#elif (VDDEE_VAL == 850)
+	#define VDDEE_VAL_REG0	0x00000010
+	#define VDDEE_VAL_REG1	0x00000010
+#elif (VDDEE_VAL == 860)
+	#define VDDEE_VAL_REG0	0x00000040
+	#define VDDEE_VAL_REG1	0x00000040
+#else
+	#error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3	((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3		((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3		((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0	((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1	((0xff800000 + (0x06 << 2)))
+
+bl2_reg_t __bl2_reg[] = {
+	/* demo, user defined override register */
+	/* eg: PWM init */
+
+	/* PWM_AO_D */
+	/* VCCK_VAL_REG: check PWM table */
+	{AO_PWM_PWM_D,        VCCK_VAL_REG,            0xffffffff,   0, BL2_INIT_STAGE_1, 0},
+	{AO_PWM_MISC_REG_CD,  ((1 << 23) | (1 << 1)),  (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+	{AO_PIN_MUX_REG1,     (3 << 20),               (0xF << 20),  0, BL2_INIT_STAGE_1, 0},
+
+	/* set BOOT_9 input */
+	//{PAD_PULL_UP_EN_REG0, 1 << 9,			1 << 9,   0, BL2_INIT_STAGE_1, 0},
+
+	/* PWM_AO_B */
+	/* VDDEE init start */
+	/* step1: CHK HW */
+	{(uint64_t)P_ASSIST_POR_CONFIG,  7,            0,            0, BL2_INIT_STAGE_PWM_CHK_HW,           0},
+
+	/* step2: match PWM config */
+	/* GPIO9[BIT7]=H use PWM_CFG0(0.67v-0.97v), =L use PWM_CFG1(0.69v-0.89v) */
+	{0x1,                 PWM_CFG0,                0,            0, BL2_INIT_STAGE_PWM_CFG_GROUP,        0},
+	{0x0,                 PWM_CFG1,                0,            0, BL2_INIT_STAGE_PWM_CFG_GROUP,        0},
+
+	/* step3: config PWM */
+	/* VDDEE_VAL_REG0: VDDEE PWM table  0.67v-0.97v*/
+	{AO_PWM_PWM_B,        VDDEE_VAL_REG0,          0xffffffff,   0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0,  0},
+	{AO_PWM_MISC_REG_AB,  ((1 << 23) | (1 << 1)),  (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0,  0},
+	{AO_PIN_MUX_REG1,     (3 << 16),               (0xF << 16),  0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0,  0},
+	/* VDDEE_VAL_REG1: VDDEE PWM table  0.69v-0.89v*/
+	{AO_PWM_PWM_B,        VDDEE_VAL_REG1,          0xffffffff,   0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1,  0},
+	{AO_PWM_MISC_REG_AB,  ((1 << 23) | (1 << 1)),  (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1,  0},
+	{AO_PIN_MUX_REG1,     (3 << 16),               (0xF << 16),  0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1,  0},
+	/* VDDEE init done */
+
+//	/* Enable 5V_EN */
+//	{GPIO_O_EN_N_REG3,    (1 << 8),                (1 << 8),     0, BL2_INIT_STAGE_1, 0},
+//	{GPIO_O_REG3,         (1 << 8),                (1 << 8),   0, BL2_INIT_STAGE_1, 0},
+//	/* Enable CPUA ,control by GPIOAO_4 */
+//	{AO_GPIO_O_EN_N,    (0 << 4),                (1 << 4),     0, BL2_INIT_STAGE_1, 0},
+//	{AO_GPIO_O,         (1 << 4),                (1 << 4),   0, BL2_INIT_STAGE_1, 0},
+//	/* Enable VCCK */
+//	{AO_SEC_REG0,         (1 << 0),                (1 << 0),     0, BL2_INIT_STAGE_1, 0},
+//	{AO_GPIO_O,           (1 << 31),               (1 << 31),    0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/hardkernel/odroidgou/gou_ext_lcd.h b/board/hardkernel/odroidgou/gou_ext_lcd.h
new file mode 100755
index 0000000000..8e21b9378e
--- /dev/null
+++ b/board/hardkernel/odroidgou/gou_ext_lcd.h
@@ -0,0 +1,84 @@
+/*
+ * board/amlogic/g12a_u200_v1/lcd_extern.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DFT_GOU_EXT_LCD_H_
+#define _DFT_GOU_EXT_LCD_H_
+
+static unsigned char ext_init_on_table_kd50t048a[LCD_EXTERN_INIT_ON_MAX] = {
+	0x13,  1, 0x01,
+	0xfd,  1, 5,	/* delay (ms) */
+	0x13,  1, 0x11,
+	0xfd,  1, 120,	/* delay (ms) */
+
+	0x29,  6, 0xFF, 0x77, 0x01, 0x00, 0x00, 0x10,
+	0x29,  3, 0xC0, 0xE9, 0x03,
+	0x29,  3, 0xC1, 0x11, 0x02,
+	0x29,  3, 0xC2, 0x31, 0x08,
+	0x23,  2, 0xCC, 0x10,
+	0x29, 17, 0xB0, 0x00, 0x0D, 0x14, 0x0D, 0x10, 0x05, 0x02, 0x08,
+	          0x08, 0x1E, 0x05, 0x13, 0x11, 0xA3, 0x29, 0x18,
+	0x29, 17, 0xB1, 0x00, 0x0C, 0x14, 0x0C, 0x10, 0x05, 0x03, 0x08,
+	          0x07, 0x20, 0x05, 0x13, 0x11, 0xA4, 0x29, 0x18,
+	0x29,  6, 0xFF, 0x77, 0x01, 0x00, 0x00, 0x11,
+	0x23,  2, 0xB0, 0x6C,
+	0x23,  2, 0xB1, 0x43,
+	0x23,  2, 0xB2, 0x07,
+	0x23,  2, 0xB3, 0x80,
+	0x23,  2, 0xB5, 0x47,
+	0x23,  2, 0xB7, 0x85,
+	0x23,  2, 0xB8, 0x20,
+	0x23,  2, 0xB9, 0x10,
+	0x23,  2, 0xC1, 0x78,
+	0x23,  2, 0xC3, 0x78,
+	0x23,  2, 0xD0, 0x88,
+	0xfd,  1, 120, /* delay (ms) */
+
+	0x29,  4, 0xE0, 0x00, 0x00, 0x02,
+	0x29, 12, 0xE1, 0x08, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x09, 0x00,
+		  0x00, 0x33, 0x33,
+	0x29, 15, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x29,  5, 0xE3, 0x00, 0x00, 0x33, 0x33,
+	0x29,  3, 0xE4, 0x44, 0x44,
+	0x29, 17, 0xE5, 0x0E, 0x60, 0xA0, 0xA0, 0x10, 0x60, 0xA0, 0xA0,
+	          0x0A, 0x60, 0xA0, 0xA0, 0x0C, 0x60, 0xA0, 0xA0,
+	0x29,  5, 0xE6, 0x00, 0x00, 0x33, 0x33,
+	0x29,  3, 0xE7, 0x44, 0x44,
+	0x29, 17, 0xE8, 0x0D, 0x60, 0xA0, 0xA0, 0x0F, 0x60, 0xA0, 0xA0,
+	          0x09, 0x60, 0xA0, 0xA0, 0x0B, 0x60, 0xA0, 0xA0,
+	0x29,  8, 0xEB, 0x02, 0x01, 0xE4, 0xE4, 0x44, 0x00, 0x40,
+	0x29,  3, 0xEC, 0x02, 0x01,
+	0x29, 17, 0xED, 0xAB, 0x89, 0x76, 0x54, 0x01, 0xFF, 0xFF, 0xFF,
+	          0xFF, 0xFF, 0xFF, 0x10, 0x45, 0x67, 0x98, 0xBA,
+	0x29,  6, 0xFF, 0x77, 0x01, 0x00, 0x00, 0x00,
+	0x23,  2, 0x3A, 0x70,
+	0x23,  2, 0x53, 0xEC,
+	0x23,  2, 0x55, 0xB3,
+	0x23,  2, 0x5E, 0xFF,
+	0x13,  1, 0x29,
+	0xfd,  1, 50,	/* delay (ms) */
+	0xff,  0,
+};
+
+static unsigned char ext_init_off_table_kd50t048a[LCD_EXTERN_INIT_OFF_MAX] = {
+	0x05, 1, 0x28,
+	0xfd, 1, 10,	/* delay (ms) */
+	0x05, 1, 0x10,
+	0xfd, 1, 150,	/* delay (ms) */
+	0xFF, 0,   /* ending flag */
+};
+
+#endif
+
diff --git a/board/hardkernel/odroidgou/gou_lcd.c b/board/hardkernel/odroidgou/gou_lcd.c
new file mode 100755
index 0000000000..5bd7492bd9
--- /dev/null
+++ b/board/hardkernel/odroidgou/gou_lcd.c
@@ -0,0 +1,350 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+#ifdef CONFIG_AML_LCD_EXTERN
+#include "gou_ext_lcd.h"
+#endif
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+	"GPIOH_4", /* panel rst */
+	"invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_KD50T048A[] = {
+	{LCD_POWER_TYPE_CPU,   0,0,10,}, /* lcd reset: 0 */
+	{LCD_POWER_TYPE_CPU,   0,1,120,}, /* lcd reset: 1 */
+	{LCD_POWER_TYPE_SIGNAL,0,0,0,},  /* signal */
+	{LCD_POWER_TYPE_MAX,   0,0,0,},  /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_KD50T048A[] = {
+	{LCD_POWER_TYPE_SIGNAL,0,0,10,},  /* signal */
+	{LCD_POWER_TYPE_CPU,   0,0,10,}, /* lcd_reset */
+	{LCD_POWER_TYPE_MAX,   0,0,0,},   /* ending flag */
+};
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+	"invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+	{/* kd50t048a*/
+	"lcd_0",LCD_MIPI,8,
+	/* basic timing */
+	480,854,542,884,12,12,0,8,4,0,
+	/* clk_attr */
+	0,0,1,28747680,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+	/* mipi_attr */
+	2,400,0,1,0,2,1,0,Rsv_val,Rsv_val,
+	/* power step */
+	lcd_power_on_step_KD50T048A, lcd_power_off_step_KD50T048A,
+	/* backlight */
+	200,255,10,128,128,
+	BL_CTRL_PWM,0,1,0,200,200,
+	BL_PWM_NEGATIVE,BL_PWM_F,180,100,50,1,1,
+	Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+	Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+	10,10,Rsv_val},
+
+	{.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+	{
+		.name = "lcd_pin",
+		.pinmux_set = {{LCD_PINMUX_END, 0x0}},
+		.pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+	},
+	{
+		.name = "invalid",
+	},
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+	{
+		.name = "bl_pwm_on_pin", //GPIOH_5
+		.pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+		.pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+	},
+	{
+		.name = "invalid",
+	},
+};
+
+static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
+	0x05, 1, 0x11,
+	0xfd, 1, 20,
+	0x05, 1, 0x29,
+	0xfd, 1, 20,
+	0xff, 0,   //ending
+};
+static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
+	0x05, 1, 0x28,
+	0xfd, 1, 10,
+	0x05, 1, 0x10,
+	0xfd, 1, 10,
+	0xff, 0,   //ending
+};
+
+static unsigned char mipi_init_on_table_KD50T048A[DSI_INIT_ON_MAX] = {//table size < 100
+	0x13, 1, 0x11,
+	0xfd, 1, 150, //delay
+	0x13, 1, 0x29,
+	0xfd, 1, 20,  //delay
+	0xff, 0,   //ending
+};
+static unsigned char mipi_init_off_table_KD50T048A[DSI_INIT_OFF_MAX] = {//table size < 50
+	0x13, 1, 0x28,
+	0xfd, 1, 10,  //delay
+	0x13, 1, 0x10,
+	0xfd, 1, 10,  //delay
+	0xff, 0,   //ending
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+	.lane_num = 2,
+	.bit_rate_max = 400, /* MHz */
+	.factor_numerator   = 0,
+	.factor_denominator = 100,
+	.operation_mode_init = 1,    /* 0=video mode, 1=command mode */
+	.operation_mode_display = 0, /* 0=video mode, 1=command mode */
+	.video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+	.clk_always_hs = 1, /* 0=disable, 1=enable */
+	.phy_switch = 0,   /* 0=auto, 1=standard, 2=slow */
+
+	.dsi_init_on  = &mipi_init_on_table[0],
+	.dsi_init_off = &mipi_init_off_table[0],
+	.extern_init = 0, /* ext_index if needed, 0xff for invalid */
+	.check_en = 0,
+	.check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+	.power_on_step = {
+		{
+			.type = LCD_POWER_TYPE_CPU,
+			.index = 0, /* point to cpu_gpio[] struct */
+			.value = 1, /* 0=output_low, 1=output_high, 2=input */
+			.delay = 10, /* unit: ms */
+		},
+		{
+			.type = LCD_POWER_TYPE_CPU,
+			.index = 0, /* point to cpu_gpio[] struct */
+			.value = 0, /* 0=output_low, 1=output_high, 2=input */
+			.delay = 20, /* unit: ms */
+		},
+		{
+			.type = LCD_POWER_TYPE_CPU,
+			.index = 0, /* point to cpu_gpio[] struct */
+			.value = 1, /* 0=output_low, 1=output_high, 2=input */
+			.delay = 20, /* unit: ms */
+		},
+		{
+			.type = LCD_POWER_TYPE_SIGNAL,
+			.index = 0, /* point to cpu_gpio[] struct */
+			.value = 1, /* 0=output_low, 1=output_high, 2=input */
+			.delay = 0, /* unit: ms */
+		},
+		{
+			.type = LCD_POWER_TYPE_MAX, /* ending flag */
+		},
+	},
+	.power_off_step = {
+		{
+			.type = LCD_POWER_TYPE_SIGNAL,
+			.index = 0, /* point to cpu_gpio[] struct */
+			.value = 0, /* 0=output_low, 1=output_high, 2=input */
+			.delay = 100, /* unit: ms */
+		},
+		{
+			.type = LCD_POWER_TYPE_CPU,
+			.index = 0, /* point to cpu_gpio[] struct */
+			.value = 0, /* 0=output_low, 1=output_high, 2=input */
+			.delay = 100, /* unit: ms */
+		},
+		{
+			.type = LCD_POWER_TYPE_MAX, /* ending flag */
+		},
+	},
+};
+
+struct lcd_config_s lcd_config_dft = {
+	.lcd_mode = LCD_MODE_TABLET,
+	.lcd_key_valid = 0,
+	.lcd_clk_path = 0,
+	.lcd_basic = {
+		.model_name = "kd50t048a",
+		.lcd_type = LCD_TYPE_MAX,
+		.lcd_bits = 8,
+		.h_active = 480,
+		.v_active = 854,
+		.h_period = 542,
+		.v_period = 884,
+
+		.screen_width   = 69,
+		.screen_height  = 139,
+	},
+
+	.lcd_timing = {
+		.clk_auto = 1,
+		.lcd_clk = 28747680,
+		.ss_level = 0,
+		.fr_adjust_type = 0,
+
+		.hsync_width = 12,
+		.hsync_bp    = 12,
+		.hsync_pol   = 0,
+		.vsync_width = 4,
+		.vsync_bp    = 8,
+		.vsync_pol   = 0,
+	},
+
+	.lcd_control = {
+		.mipi_config= &lcd_mipi_config,
+	},
+	.lcd_power = &lcd_power_ctrl,
+
+	.pinctrl_ver = 2,
+	.lcd_pinmux = lcd_pinmux_ctrl,
+	.pinmux_set = {{LCD_PINMUX_END, 0x0}},
+	.pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+	"invalid", /* ending flag */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+	.lcd_ext_key_valid = 0,
+	.lcd_ext_num = 0,
+	.i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
+	.pinmux_set = {{LCD_PINMUX_END, 0x0}},
+	.pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+	{ /* kd50t048a */
+		.index = 0,
+		.name = "mipi_kd50t048a",
+		.type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+		.status = 1, /* 0=disable, 1=enable */
+		.cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+		.table_init_on = ext_init_on_table_kd50t048a,
+		.table_init_on_cnt = sizeof(ext_init_on_table_kd50t048a),
+		.table_init_off = ext_init_off_table_kd50t048a,
+		.table_init_off_cnt = sizeof(ext_init_off_table_kd50t048a),
+	},
+	{
+		.index = LCD_EXTERN_INDEX_INVALID,
+	},
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+	.name = "default",
+	.bl_key_valid = 0,
+
+	.level_default = 100,
+	.level_min = 10,
+	.level_max = 255,
+	.level_mid = 128,
+	.level_mid_mapping = 128,
+	.level = 0,
+
+	.method = BL_CTRL_MAX,
+	.power_on_delay = 200,
+	.power_off_delay = 200,
+
+	.en_gpio = 0xff,
+	.en_gpio_on = 1,
+	.en_gpio_off = 0,
+
+	.bl_pwm = NULL,
+	.bl_pwm_combo0 = NULL,
+	.bl_pwm_combo1 = NULL,
+	.pwm_on_delay = 10,
+	.pwm_off_delay = 10,
+
+	.bl_extern_index = 0xff,
+
+	.pinctrl_ver = 2,
+	.bl_pinmux = bl_pinmux_ctrl,
+	.pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+	.pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX];
+static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX];
+struct bl_extern_config_s bl_extern_config_dtf = {
+	.index = BL_EXTERN_INDEX_INVALID,
+	.name = "none",
+	.type = BL_EXTERN_MAX,
+	.i2c_addr = 0xff,
+	.i2c_bus = BL_EXTERN_I2C_BUS_MAX,
+	.dim_min = 10,
+	.dim_max = 255,
+
+	.init_loaded = 0,
+	.cmd_size = 0xff,
+	.init_on = bl_ext_init_on,
+	.init_off = bl_ext_init_off,
+	.init_on_cnt = sizeof(bl_ext_init_on),
+	.init_off_cnt = sizeof(bl_ext_init_off),
+};
+#endif
+
+void lcd_config_bsp_init(void)
+{
+	int i, j;
+
+	lcd_mipi_config.dsi_init_on = mipi_init_on_table_KD50T048A;
+	lcd_mipi_config.dsi_init_off = mipi_init_off_table_KD50T048A;
+
+	for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+		if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+			break;
+		strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+	}
+	for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+		strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+	for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+		if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+			break;
+		strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+	}
+	for (j = i; j < BL_GPIO_NUM_MAX; j++)
+		strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+	for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+		if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+			break;
+	}
+	ext_common_dft.lcd_ext_num = i;
+
+	for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+		if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+			break;
+		strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+	}
+	for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+		strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/hardkernel/odroidgou/odroidgou.c b/board/hardkernel/odroidgou/odroidgou.c
new file mode 100755
index 0000000000..586d3a34f3
--- /dev/null
+++ b/board/hardkernel/odroidgou/odroidgou.c
@@ -0,0 +1,430 @@
+/*
+ * board/hardkernel/odroidn2/odroidn2.c
+ *
+ * (C) Copyright 2018 Hardkernel Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <amlogic/i2c.h>
+#include <aml_i2c.h>
+#include <amlogic/odroid_pmic.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#ifdef CONFIG_AML_SPIFC
+#include <amlogic/spifc.h>
+#endif
+
+#include <odroid-common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket*  eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+	//UART in "Always On Module"
+	//GPIOAO_0==tx,GPIOAO_1==rx
+	//setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+	return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+#ifdef ETHERNET_EXTERNAL_PHY
+
+static int dwmac_meson_cfg_drive_strength(void)
+{
+	writel(0xaaaaaaa5, P_PAD_DS_REG4A);
+	return 0;
+}
+
+static void setup_net_chip_ext(void)
+{
+	eth_aml_reg0_t eth_reg0;
+	writel(0x11111111, P_PERIPHS_PIN_MUX_6);
+	writel(0x111111, P_PERIPHS_PIN_MUX_7);
+
+	eth_reg0.d32 = 0;
+	eth_reg0.b.phy_intf_sel = 1;
+	eth_reg0.b.rx_clk_rmii_invert = 0;
+	eth_reg0.b.rgmii_tx_clk_src = 0;
+	eth_reg0.b.rgmii_tx_clk_phase = 1;
+	eth_reg0.b.rgmii_tx_clk_ratio = 4;
+	eth_reg0.b.phy_ref_clk_enable = 1;
+	eth_reg0.b.clk_rmii_i_invert = 0;
+	eth_reg0.b.clk_en = 1;
+	eth_reg0.b.adj_enable = 0;
+	eth_reg0.b.adj_setup = 0;
+	eth_reg0.b.adj_delay = 0;
+	eth_reg0.b.adj_skew = 0;
+	eth_reg0.b.cali_start = 0;
+	eth_reg0.b.cali_rise = 0;
+	eth_reg0.b.cali_sel = 0;
+	eth_reg0.b.rgmii_rx_reuse = 0;
+	eth_reg0.b.eth_urgent = 0;
+	setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+	setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3);
+	/* power on memory */
+	clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+	return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int  sd_emmc_init(unsigned port)
+{
+	switch (port)
+	{
+		case SDIO_PORT_A:
+			break;
+		case SDIO_PORT_B:
+			//todo add card detect
+			/* check card detect */
+			clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
+			setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
+			setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
+			setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
+			break;
+		case SDIO_PORT_C:
+			//enable pull up
+			//clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+			break;
+		default:
+			break;
+	}
+
+	return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+	cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+	switch (port)
+	{
+		case SDIO_PORT_A:
+			break;
+		case SDIO_PORT_B:
+			//            clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+			//            clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+			/// @todo NOT FINISH
+			break;
+		case SDIO_PORT_C:
+			break;
+		default:
+			break;
+	}
+	return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+	/// @todo NOT FINISH
+	switch (port)
+	{
+		case SDIO_PORT_A:
+			break;
+		case SDIO_PORT_B:
+			//            setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+			//            clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+			break;
+		case SDIO_PORT_C:
+			break;
+		default:
+			break;
+	}
+	return;
+}
+
+// #define CONFIG_TSD      1
+static void board_mmc_register(unsigned port)
+{
+	struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+	if (aml_priv == NULL)
+		return;
+
+	aml_priv->sd_emmc_init=sd_emmc_init;
+	aml_priv->sd_emmc_detect=sd_emmc_detect;
+	aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+	aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+	aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+	aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+	if (NULL == aml_priv->desc_buf)
+		printf(" desc_buf Dma alloc Fail!\n");
+	else
+		printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+	sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t	*bis)
+{
+	board_mmc_register(SDIO_PORT_C);	// eMMC
+	board_mmc_register(SDIO_PORT_B);	// SD card
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_AML
+struct aml_i2c_platform g_aml_i2c_plat[] = {
+{
+	.wait_count         = 1000000,
+	.wait_ack_interval  = 5,
+	.wait_read_interval = 5,
+	.wait_xfer_interval = 5,
+	.master_no          = AML_I2C_MASTER_AO,
+	.use_pio            = 0,
+	.master_i2c_speed   = AML_I2C_SPPED_400K,
+	.master_ao_pinmux = {
+		.scl_reg    = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_2_REG,
+		.scl_bit    = MESON_I2C_MASTER_AO_GPIOAO_2_BIT,
+		.sda_reg    = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_3_REG,
+		.sda_bit    = MESON_I2C_MASTER_AO_GPIOAO_3_BIT,
+	},
+},
+};
+
+static void board_i2c_init(void)
+{
+	//Amlogic I2C controller initialized
+	//note: it must be call before any I2C operation
+	//aml_i2c_init();
+
+	extern void aml_i2c_set_ports(struct aml_i2c_platform *i2c_plat);
+	aml_i2c_set_ports(g_aml_i2c_plat);
+}
+
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+	/* setup the default voltage : VDD_EE */
+	if (board_revision() < BOARD_REVISION(2018, 12, 6))
+		writel(0x100016, AO_PWM_PWM_B);	/* 0.8420V */
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+#include <asm/arch/usb-v2.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM	2
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
+#define CONFIG_GXL_USB_U3_PORT_NUM	1
+#else
+#define CONFIG_GXL_USB_U3_PORT_NUM	0
+#endif
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+	CONFIG_GXL_XHCI_BASE,
+	USB_ID_MODE_HARDWARE,
+	gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
+	CONFIG_GXL_USB_PHY2_BASE,
+	CONFIG_GXL_USB_PHY3_BASE,
+	CONFIG_GXL_USB_U2_PORT_NUM,
+	CONFIG_GXL_USB_U3_PORT_NUM,
+	.usb_phy2_pll_base_addr = {
+		CONFIG_USB_PHY_20,
+		CONFIG_USB_PHY_21,
+	}
+};
+
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_7: NOR_WPn:reg0[31:28]=3
+ * BOOT_14: NOR_CS:reg1[27:24]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+	unsigned int val;
+
+	val = readl(P_PERIPHS_PIN_MUX_0);
+	val &= ~(0xfffff << 12);
+	if (enable)
+		val |= 0x33333 << 12;
+	writel(val, P_PERIPHS_PIN_MUX_0);
+
+	val = readl(P_PERIPHS_PIN_MUX_1);
+	val &= ~(0xf << 24);
+	writel(val, P_PERIPHS_PIN_MUX_1);
+	return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+	.reg = 0xffd14000,
+	.mem_map = 0xf6000000,
+	.pinctrl_enable = spifc_pinctrl_enable,
+	.num_chipselect = SPIFC_NUM_CS,
+	.cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+	.name = "spifc",
+	.platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+int board_init(void)
+{
+	board_led_alive(1);
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+	board_usb_pll_disable(&g_usb_config_GXL_skt);
+	board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+	return 0;
+}
+
+#if !defined(CONFIG_FASTBOOT_FLASH_MMC_DEV)
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV		0
+#endif
+
+extern void cvbs_init(void);
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if defined(CONFIG_FASTBOOT_FLASH_MMC_DEV)
+	/* select the default mmc device */
+	int mmc_devnum = CONFIG_FASTBOOT_FLASH_MMC_DEV;
+
+	if (get_boot_device() == BOOT_DEVICE_EMMC)
+		mmc_devnum = 0;
+	else if (get_boot_device() == BOOT_DEVICE_SD)
+		mmc_devnum = 1;
+
+	/* select the default mmc device */
+	mmc_select_hwpart(mmc_devnum, 0);
+#endif
+#ifdef CONFIG_SYS_I2C_AML
+	board_i2c_init();
+#endif
+
+#ifdef CONFIG_ODROID_PMIC
+	odroid_pmic_init();
+#endif
+
+#ifdef CONFIG_AML_VPU
+	vpu_probe();
+#endif
+	vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+	hdmi_tx_set_hdmi_5v();
+	hdmi_tx_init();
+#endif
+
+#ifdef CONFIG_AML_CVBS
+	run_command("cvbs init; cvbs output 480cvbs", 0);
+	board_cvbs_probe();
+#endif
+
+#ifdef CONFIG_AML_LCD
+	lcd_probe();
+#endif
+
+	setenv("variant", board_is_odroidgou() ? "gou" : "n2");
+	board_set_dtbfile("meson64_odroid%s.dtb");
+
+	if (get_boot_device() == BOOT_DEVICE_SPI) {
+		setenv("bootdelay", "0");
+		setenv("bootcmd", "run boot_spi");
+	}
+
+	/* boot logo display - 1080p60hz */
+	run_command("showlogo", 0);
+	usbhost_early_poweron();
+
+	return 0;
+}
+#endif
+
+/* SECTION_SHIFT is 29 that means 512MB size */
+#define SECTION_SHIFT		29
+phys_size_t get_effective_memsize(void)
+{
+	phys_size_t size_aligned;
+
+	size_aligned = (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+	size_aligned = ((size_aligned >> SECTION_SHIFT) << SECTION_SHIFT);
+
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+	size_aligned = size_aligned - CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+
+	return size_aligned;
+}
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index 22db1bb47c..272d654f8b 100644..100755
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -1667,7 +1667,7 @@ static int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc,
  * on error.
  */
 #if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS) || \
-		defined(CONFIG_DM_I2C)
+		defined(CONFIG_DM_I2C) || defined(CONFIG_SYS_I2C_AML)
 static int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc,
 				char * const argv[])
 {
@@ -1809,7 +1809,7 @@ static cmd_tbl_t cmd_i2c_sub[] = {
 	U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""),
 #endif
 	U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
-#if defined(CONFIG_SYS_I2C) || \
+#if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_AML) || \
 	defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
 	U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
 #endif  /* CONFIG_I2C_MULTI_BUS */
@@ -1872,11 +1872,11 @@ static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 /***************************************************/
 #ifdef CONFIG_SYS_LONGHELP
 static char i2c_help_text[] =
-#if defined(CONFIG_SYS_I2C)
+#if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_AML)
 	"bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n"
 #endif
 	"crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
-#if defined(CONFIG_SYS_I2C) || \
+#if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_AML) || \
 	defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
 	"i2c dev [dev] - show or set current I2C bus\n"
 #endif  /* CONFIG_I2C_MULTI_BUS */
diff --git a/configs/odroidgou_defconfig b/configs/odroidgou_defconfig
new file mode 100755
index 0000000000..ea4529baac
--- /dev/null
+++ b/configs/odroidgou_defconfig
@@ -0,0 +1,7 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_G12B=y
+CONFIG_ODROID_GOU=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/drivers/display/lcd/lcd_extern/Makefile b/drivers/display/lcd/lcd_extern/Makefile
index 11709ba8ee..302f9e85a0 100644
--- a/drivers/display/lcd/lcd_extern/Makefile
+++ b/drivers/display/lcd/lcd_extern/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_AML_LCD_EXTERN_MIPI_TV070WSM) += mipi_TV070WSM.o
 obj-$(CONFIG_AML_LCD_EXTERN_MIPI_ST7701)   += mipi_ST7701.o
 obj-$(CONFIG_AML_LCD_EXTERN_MIPI_P070ACB)  += mipi_P070ACB.o
 obj-$(CONFIG_AML_LCD_EXTERN_MIPI_TL050FHV02CT)  += mipi_TL050FHV02CT.o
+obj-$(CONFIG_AML_LCD_EXTERN_MIPI_KD50T048A)   += mipi_kd50t048a.o
diff --git a/drivers/display/lcd/lcd_extern/lcd_extern.c b/drivers/display/lcd/lcd_extern/lcd_extern.c
index fbf4ddf3cb..8c1a53c543 100644
--- a/drivers/display/lcd/lcd_extern/lcd_extern.c
+++ b/drivers/display/lcd/lcd_extern/lcd_extern.c
@@ -1443,6 +1443,10 @@ static int aml_lcd_extern_add_mipi(struct aml_lcd_extern_driver_s *ext_drv)
 #ifdef CONFIG_AML_LCD_EXTERN_MIPI_TL050FHV02CT
 		ret = aml_lcd_extern_mipi_tl050fhv02ct_probe(ext_drv);
 #endif
+	} else if (strcmp(ext_drv->config->name, "mipi_kd50t048a") == 0) {
+#ifdef CONFIG_AML_LCD_EXTERN_MIPI_KD50T048A
+		ret = aml_lcd_extern_mipi_kd50t048a_probe(ext_drv);
+#endif
 	} else {
 		EXTERR("invalid driver name: %s\n", ext_drv->config->name);
 	}
@@ -1622,6 +1626,12 @@ static int aml_lcd_extern_add_driver_default(int index,
 		goto add_driver_default_end;
 	}
 #endif
+#ifdef CONFIG_AML_LCD_EXTERN_MIPI_KD50T048A
+	if (strcmp(ext_drv->config->name, "mipi_kd50t048a") == 0) {
+		ret = aml_lcd_extern_mipi_kd50t048a_probe(ext_drv);
+		goto add_driver_default_end;
+	}
+#endif
 
 add_driver_default_end:
 	if (ret) {
diff --git a/drivers/display/lcd/lcd_extern/lcd_extern.h b/drivers/display/lcd/lcd_extern/lcd_extern.h
index d343e650b1..64c38a3225 100644
--- a/drivers/display/lcd/lcd_extern/lcd_extern.h
+++ b/drivers/display/lcd/lcd_extern/lcd_extern.h
@@ -93,6 +93,9 @@ extern int aml_lcd_extern_mipi_p070acb_probe(struct aml_lcd_extern_driver_s *ext
 #ifdef CONFIG_AML_LCD_EXTERN_MIPI_TL050FHV02CT
 extern int aml_lcd_extern_mipi_tl050fhv02ct_probe(struct aml_lcd_extern_driver_s *ext_drv);
 #endif
+#ifdef CONFIG_AML_LCD_EXTERN_MIPI_KD50T048A
+extern int aml_lcd_extern_mipi_kd50t048a_probe(struct aml_lcd_extern_driver_s *ext_drv);
+#endif
 
 #endif
 
diff --git a/drivers/display/lcd/lcd_extern/mipi_kd50t048a.c b/drivers/display/lcd/lcd_extern/mipi_kd50t048a.c
new file mode 100755
index 0000000000..9fce0b10fb
--- /dev/null
+++ b/drivers/display/lcd/lcd_extern/mipi_kd50t048a.c
@@ -0,0 +1,180 @@
+/*
+ * drivers/display/lcd/lcd_extern/mipi_kd50t048a.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/gpio.h>
+#ifdef CONFIG_OF_LIBFDT
+#include <libfdt.h>
+#endif
+#include <amlogic/aml_lcd.h>
+#include <amlogic/aml_lcd_extern.h>
+#include "lcd_extern.h"
+
+#define LCD_EXTERN_NAME			"mipi_kd50t048a"
+#define LCD_EXTERN_TYPE			LCD_EXTERN_MIPI
+
+/******************** mipi command ********************/
+/* format:  data_type, cmd_size, data.... */
+/* 	data_type=0xff,
+ *		0 < cmd_size < 0xff means delay ms,
+ *		cmd_size=0 or 0xff means ending.
+ *	data_type=0xf0, for gpio control
+ *		data0=gpio_index, data1=gpio_value.
+ *		data0=gpio_index, data1=gpio_value, data2=delay.
+ *	data_type=0xfd, for delay ms
+ *		data0=delay, data_1=delay, ..., data_n=delay.
+ */
+//******************************************************//
+//static unsigned char mipi_init_on_table[] = {
+//	0x05, 3, 0x05, 0x01, 0x01,
+//	0x05, 3, 0xFA, 0x01, 0x11,
+//	0x39, 8, 0x00, 0x06, 0xFF, 0x77, 0x01, 0x00, 0x00, 0x10,
+//	0x15, 5, 0x00, 0x03, 0xC0, 0xE9, 0x03,
+//	0x15, 5, 0x00, 0x03, 0xC1, 0x11, 0x02,
+//	0x15, 5, 0x00, 0x03, 0xC2, 0x31, 0x08,
+//	0x15, 4, 0x00, 0x02, 0xCC, 0x10,
+//	0x39,19, 0x00, 0x11, 0xB0, 0x00, 0x0D, 0x14, 0x0D, 0x10, 0x05, 0x02, 0x08, 0x08, 0x1E, 0x05, 0x13, 0x11, 0xA3, 0x29, 0x18,
+//	0x39,19, 0x00, 0x11, 0xB1, 0x00, 0x0C, 0x14, 0x0C, 0x10, 0x05, 0x03, 0x08, 0x07, 0x20, 0x05, 0x13, 0x11, 0xA4, 0x29, 0x18,
+//	0x39, 8, 0x00, 0x06, 0xFF, 0x77, 0x01, 0x00, 0x00, 0x11,
+//	0x15, 4, 0x00, 0x02, 0xB0, 0x6C,
+//	0x15, 4, 0x00, 0x02, 0xB1, 0x43,
+//	0x15, 4, 0x00, 0x02, 0xB2, 0x07,
+//	0x15, 4, 0x00, 0x02, 0xB3, 0x80,
+//	0x15, 4, 0x00, 0x02, 0xB5, 0x47,
+//	0x15, 4, 0x00, 0x02, 0xB7, 0x85,
+//	0x15, 4, 0x00, 0x02, 0xB8, 0x20,
+//	0x15, 4, 0x00, 0x02, 0xB9, 0x10,
+//	0x15, 4, 0x00, 0x02, 0xC1, 0x78,
+//	0x15, 4, 0x00, 0x02, 0xC3, 0x78,
+//	0x15, 4, 0xFA, 0x02, 0xD0, 0x88,
+//	0x39, 6, 0x00, 0x04, 0xE0, 0x00, 0x00, 0x02,
+//	0x39,14, 0x00, 0x0C, 0xE1, 0x08, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x09, 0x00, 0x00, 0x33, 0x33,
+//	0x39,17, 0x00, 0x0F, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+//	0x39, 7, 0x00, 0x05, 0xE3, 0x00, 0x00, 0x33, 0x33,
+//	0x15, 5, 0x00, 0x03, 0xE4, 0x44, 0x44,
+//	0x39,19, 0x00, 0x11, 0xE5, 0x0E, 0x60, 0xA0, 0xA0, 0x10, 0x60, 0xA0, 0xA0, 0x0A, 0x60, 0xA0, 0xA0, 0x0C, 0x60, 0xA0, 0xA0,
+//	0x39, 7, 0x00, 0x05, 0xE6, 0x00, 0x00, 0x33, 0x33,
+//	0x15, 5, 0x00, 0x03, 0xE7, 0x44, 0x44,
+//	0x39,19, 0x00, 0x11, 0xE8, 0x0D, 0x60, 0xA0, 0xA0, 0x0F, 0x60, 0xA0, 0xA0, 0x09, 0x60, 0xA0, 0xA0, 0x0B, 0x60, 0xA0, 0xA0,
+//	0x39,10, 0x00, 0x08, 0xEB, 0x02, 0x01, 0xE4, 0xE4, 0x44, 0x00, 0x40,
+//	0x15, 5, 0x00, 0x03, 0xEC, 0x02, 0x01,
+//	0x39,19, 0x00, 0x11, 0xED, 0xAB, 0x89, 0x76, 0x54, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x10, 0x45, 0x67, 0x98, 0xBA,
+//	0x39, 8, 0x00, 0x06, 0xFF, 0x77, 0x01, 0x00, 0x00, 0x00,
+//	0x15, 4, 0x00, 0x02, 0x3A, 0x70,
+//	0x15, 4, 0x00, 0x02, 0x53, 0xEC,
+//	0x15, 4, 0x00, 0x02, 0x55, 0xB3,
+//	0x15, 4, 0x00, 0x02, 0x5E, 0xFF,
+//	0x05, 3, 0x32, 0x01, 0x29,
+//	0xfd, 1, 200,    /* delay(ms) */
+//	0xff, 0,   /* ending */
+//};
+//
+//static unsigned char mipi_init_off_table[] = {
+//	0x05, 1, 0x28, /* display off */
+//	0xfd, 1, 10,   /* delay 10ms */
+//	0x05, 1, 0x10, /* sleep in */
+//	0xfd, 1, 150,  /* delay 150ms */
+//	0xff, 0,   /* ending */
+//};
+
+static unsigned char mipi_init_on_table[] = {
+	0x13, 1, 0x01,
+	0xfd, 1, 5,	/* delay (ms) */
+	0x13, 1, 0x11,
+	0xfd, 1, 250,	/* delay (ms) */
+
+	0x29, 6, 0xFF, 0x77, 0x01, 0x00, 0x00, 0x10,
+	0x29, 3, 0xC0, 0xE9, 0x03,
+	0x29, 3, 0xC1, 0x11, 0x02,
+	0x29, 3, 0xC2, 0x31, 0x08,
+	0x23, 2, 0xCC, 0x10,
+	0x29,17, 0xB0, 0x00, 0x0D, 0x14, 0x0D, 0x10, 0x05, 0x02, 0x08,
+	         0x08, 0x1E, 0x05, 0x13, 0x11, 0xA3, 0x29, 0x18,
+	0x29,17, 0xB1, 0x00, 0x0C, 0x14, 0x0C, 0x10, 0x05, 0x03, 0x08,
+	         0x07, 0x20, 0x05, 0x13, 0x11, 0xA4, 0x29, 0x18,
+	0x29, 6, 0xFF, 0x77, 0x01, 0x00, 0x00, 0x11,
+	0x23, 2, 0xB0, 0x6C,
+	0x23, 2, 0xB1, 0x43,
+	0x23, 2, 0xB2, 0x07,
+	0x23, 2, 0xB3, 0x80,
+	0x23, 2, 0xB5, 0x47,
+	0x23, 2, 0xB7, 0x85,
+	0x23, 2, 0xB8, 0x20,
+	0x23, 2, 0xB9, 0x10,
+	0x23, 2, 0xC1, 0x78,
+	0x23, 2, 0xC3, 0x78,
+	0x23, 2, 0xD0, 0x88,
+	0xfd, 1, 250,	/* delay (ms) */
+
+	0x29, 4, 0xE0, 0x00, 0x00, 0x02,
+	0x29,12, 0xE1, 0x08, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x09, 0x00, 0x00, 0x33, 0x33,
+	0x29,15, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x29, 5, 0xE3, 0x00, 0x00, 0x33, 0x33,
+	0x29, 3, 0xE4, 0x44, 0x44,
+	0x29,17, 0xE5, 0x0E, 0x60, 0xA0, 0xA0, 0x10, 0x60, 0xA0, 0xA0,
+	         0x0A, 0x60, 0xA0, 0xA0, 0x0C, 0x60, 0xA0, 0xA0,
+	0x29, 5, 0xE6, 0x00, 0x00, 0x33, 0x33,
+	0x29, 3, 0xE7, 0x44, 0x44,
+	0x29,17, 0xE8, 0x0D, 0x60, 0xA0, 0xA0, 0x0F, 0x60, 0xA0, 0xA0,
+	         0x09, 0x60, 0xA0, 0xA0, 0x0B, 0x60, 0xA0, 0xA0,
+	0x29, 8, 0xEB, 0x02, 0x01, 0xE4, 0xE4, 0x44, 0x00, 0x40,
+	0x29, 3, 0xEC, 0x02, 0x01,
+	0x29,17, 0xED, 0xAB, 0x89, 0x76, 0x54, 0x01, 0xFF, 0xFF, 0xFF,
+	         0xFF, 0xFF, 0xFF, 0x10, 0x45, 0x67, 0x98, 0xBA,
+	0x29, 6, 0xFF, 0x77, 0x01, 0x00, 0x00, 0x00,
+	0x23, 2, 0x3A, 0x70,
+	0x23, 2, 0x53, 0xEC,
+	0x23, 2, 0x55, 0xB3,
+	0x23, 2, 0x5E, 0xFF,
+	0x13, 1, 0x29,
+	0xfd, 1, 50,	/* delay (ms) */
+	0xff, 0,   	/* ending flag */
+};
+
+static unsigned char mipi_init_off_table[] = {
+	0x05, 1, 0x28,	/* display off */
+	0xfd, 1, 10,	/* delay 10ms */
+	0x05, 1, 0x10,	/* sleep in */
+	0xfd, 1, 150,	/* delay 150ms */
+	0xff, 0,   	/* ending flag */
+};
+
+static int lcd_extern_driver_update(struct aml_lcd_extern_driver_s *ext_drv)
+{
+	if (ext_drv == NULL) {
+		EXTERR("%s driver is null\n", LCD_EXTERN_NAME);
+		return -1;
+	}
+
+	ext_drv->config->cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC;
+	ext_drv->config->table_init_on  = &mipi_init_on_table[0];
+	ext_drv->config->table_init_on_cnt  = sizeof(mipi_init_on_table);
+	ext_drv->config->table_init_off = &mipi_init_off_table[0];
+	ext_drv->config->table_init_off_cnt  = sizeof(mipi_init_off_table);
+
+	return 0;
+}
+
+int aml_lcd_extern_mipi_kd50t048a_probe(struct aml_lcd_extern_driver_s *ext_drv)
+{
+	int ret = 0;
+
+	ret = lcd_extern_driver_update(ext_drv);
+
+	if (lcd_debug_print_flag)
+		EXTPR("%s: %d\n", __func__, ret);
+	return ret;
+}
diff --git a/drivers/display/lcd/lcd_tablet/lcd_tablet.c b/drivers/display/lcd/lcd_tablet/lcd_tablet.c
index f6896ecb06..f218c22118 100644
--- a/drivers/display/lcd/lcd_tablet/lcd_tablet.c
+++ b/drivers/display/lcd/lcd_tablet/lcd_tablet.c
@@ -569,7 +569,7 @@ static int lcd_config_load_from_bsp(struct lcd_config_s *pconf)
 		lcd_mipi_dsi_init_table_check_bsp(pconf->lcd_control.mipi_config, 0);
 
 		if (ext_lcd->lcd_spc_val9 == Rsv_val)
-			pconf->lcd_control.mipi_config->extern_init = 0xff;
+			pconf->lcd_control.mipi_config->extern_init = 0;
 		else
 			pconf->lcd_control.mipi_config->extern_init = ext_lcd->lcd_spc_val9;
 	}
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 8b617e43ff..629127af4d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -35,3 +35,4 @@ obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
 obj-$(CONFIG_SYS_I2C_AML) += aml_i2c.o
 obj-$(CONFIG_SYS_I2C_AML_IS31F123XX) += aml_is31fl32xx.o
 obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
+obj-$(CONFIG_ODROID_PMIC) += odroid_pmic.o
\ No newline at end of file
diff --git a/drivers/i2c/odroid_pmic.c b/drivers/i2c/odroid_pmic.c
new file mode 100755
index 0000000000..217eaff24b
--- /dev/null
+++ b/drivers/i2c/odroid_pmic.c
@@ -0,0 +1,90 @@
+/*
+ * drivers/i2c/odroid_pmic.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * add by: renjun.xu@amlogic.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/gpio.h>
+#ifdef CONFIG_OF_LIBFDT
+#include <libfdt.h>
+#endif
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#endif
+#include <amlogic/odroid_pmic.h>
+
+static int rk818_i2c_write(int32_t command, uint8_t val)
+{
+	int ret = 0;
+	uint8_t buf[2] = {0};
+	struct i2c_msg msg;
+
+	msg.addr = RK818_ADDR;
+	msg.flags = 0;
+	msg.len = sizeof(buf);
+	msg.buf = buf;
+
+	buf[0] = command & 0xff;
+	buf[1] = val & 0xff;
+
+	ret = aml_i2c_xfer(&msg, 1);
+	if (ret < 0)
+		printf("i2c write failed [addr 0x%02x]\n", msg.addr);
+
+	return ret;
+}
+
+static int rk817_i2c_write(int32_t command, uint8_t val)
+{
+	int ret = 0;
+	uint8_t buf[2] = {0};
+	struct i2c_msg msg;
+
+	msg.addr = RK817_ADDR;
+	msg.flags = 0;
+	msg.len = sizeof(buf);
+	msg.buf = buf;
+
+	buf[0] = command & 0xff;
+	buf[1] = val & 0xff;
+
+	ret = aml_i2c_xfer(&msg, 1);
+	if (ret < 0)
+		printf("i2c write failed [addr 0x%02x]\n", msg.addr);
+
+	return ret;
+}
+
+void odroid_pmic_init(void)
+{
+	printf("enter odroid_pmic_init.\n");
+	
+	/* RK817 LDO8 default : 3.0V */
+	rk817_i2c_write(0xda, 0x60);
+	rk817_i2c_write(0xdb, 0x60);
+	
+	/* RK817 LDO8 ON */
+	rk817_i2c_write(0xb3, 0x88);
+
+	//rk817_i2c_write(0xb2, 0x74);
+	//rk817_i2c_write(0xb2, 0x74);
+	//rk817_i2c_write(0xb2, 0x74);
+
+	/* RK818 LDO6 */
+	rk818_i2c_write(0x45, 0x1f);
+	//rk818_i2c_write(0x24, 0x50);
+}
diff --git a/fip/Makefile b/fip/Makefile
index b374bd63a8..8c45e9763d 100644
--- a/fip/Makefile
+++ b/fip/Makefile
@@ -128,6 +128,19 @@ endif
 	$(call encrypt_step, --bl2sig \
 			--input $(buildtree)/fip/bl2_new.bin \
 			--output $(buildtree)/fip/bl2.n.bin.sig)
+
+ifeq ($(CONFIG_ODROID_GOU),y)
+	$(call encrypt_step,--bootmk $(FIP_BL32_PROCESS) $(V3_PROCESS_FLAG) \
+			--bl2 $(buildtree)/fip/bl2.n.bin.sig \
+			--bl30 $(buildtree)/fip/bl30_new.bin.enc \
+			--bl31 $(buildtree)/fip/bl31.$(BL3X_SUFFIX).enc \
+			--bl33 $(buildtree)/fip/bl33.bin.enc \
+			--ddrfw1 $(buildsrc)/fip/$(SOC)/lpddr4_1d.fw \
+			--ddrfw2 $(buildsrc)/fip/$(SOC)/lpddr4_2d.fw \
+			--ddrfw4 $(buildsrc)/fip/$(SOC)/piei.fw \
+			--ddrfw8 $(buildsrc)/fip/$(SOC)/$(DDR_FW_NAME) \
+			--output $(FUSING_FOLDER)/u-boot.bin)
+else
 	$(call encrypt_step,--bootmk $(FIP_BL32_PROCESS) $(V3_PROCESS_FLAG) \
 			--bl2 $(buildtree)/fip/bl2.n.bin.sig \
 			--bl30 $(buildtree)/fip/bl30_new.bin.enc \
@@ -138,6 +151,8 @@ endif
 			--ddrfw4 $(buildsrc)/fip/$(SOC)/piei.fw \
 			--ddrfw8 $(buildsrc)/fip/$(SOC)/$(DDR_FW_NAME) \
 			--output $(FUSING_FOLDER)/u-boot.bin)
+endif
+
 ifeq ($(CONFIG_AML_CRYPTO_UBOOT),y)
 	$(call encrypt_step, --efsgen --amluserkey $(AML_USER_KEY) \
 			--output $(buildtree)/fip/u-boot.bin.encrypt.efuse $(V3_PROCESS_FLAG))
diff --git a/include/amlogic/odroid_pmic.h b/include/amlogic/odroid_pmic.h
new file mode 100755
index 0000000000..e66c592ec3
--- /dev/null
+++ b/include/amlogic/odroid_pmic.h
@@ -0,0 +1,9 @@
+#ifndef __ODROID_PMIC
+#define __ODROID_PMIC
+
+#define RK817_ADDR 0x20
+#define RK818_ADDR 0x1c
+
+void odroid_pmic_init(void);
+
+#endif
diff --git a/include/configs/odroidgou.h b/include/configs/odroidgou.h
new file mode 100755
index 0000000000..33c331d51d
--- /dev/null
+++ b/include/configs/odroidgou.h
@@ -0,0 +1,210 @@
+/*
+ * include/configs/odroidgou.h
+ *
+ * (C) Copyright 2021 Hardkernel Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+
+#ifndef __ODROIDGOU_H__
+#define __ODROIDGOU_H__
+
+#define CONFIG_DEVICE_PRODUCT		"odroidgou"
+#define ODROID_BOARD_UUID		"909802f2-a1dd-11e8-98d0-529269fb1459"
+
+/* configs for CEC */
+//define CONFIG_CEC_OSD_NAME		"ODROID-GOU"
+//#define CONFIG_CEC_WAKEUP
+
+#include "odroid-g12-common.h"
+
+#undef CONFIG_AML_SPIFC
+#undef ETHERNET_INTERNAL_PHY
+#undef ETHERNET_EXTERNAL_PHY
+#undef CONFIG_AML_CVBS
+
+#undef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_ODROID_PMIC 1
+
+#define CONFIG_AML_LCD    1
+#define CONFIG_AML_LCD_TABLET 1
+#define CONFIG_AML_LCD_EXTERN 1
+#define CONFIG_AML_LCD_EXTERN_MIPI_KD50T048A 1
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+        ENV_PXE_DEFAULT \
+        ENV_MMC_DEFAULT \
+        ENV_MMC_LIST_DEFAULT \
+	ENV_USB_DEFAULT \
+	ENV_USB_LIST_DEFAULT \
+	ENV_BOOTSCRIPTS_DEFAULT \
+	ENV_BOOT_ORDER_DEFAULT \
+	ENV_BOOT_DEFAULT \
+	ENV_BOOT_ATTEMPT_DEFAULT \
+	"console=" CONFIG_DEFAULT_CONSOLE \
+        "loadaddr=0x1080000\0"\
+        "panel_type=lcd_0\0" \
+        "outputmode=panel\0" \
+        "hdmimode=1080p60hz\0" \
+        "display_width=1920\0" \
+        "display_height=1080\0" \
+        "display_bpp=24\0" \
+        "display_color_index=24\0" \
+        "display_layer=osd0\0" \
+        "display_color_fg=0xffff\0" \
+        "display_color_bg=0\0" \
+        "dtb_mem_addr=0x1000000\0" \
+        "cramfsaddr=0x20000000\0" \
+        "fb_addr=0x3d800000\0" \
+        "fb_width=1920\0" \
+        "fb_height=1080\0" \
+        "fdt_high=0x20000000\0"\
+        "fdt_addr_r=0x1000000\0" \
+        "kernel_addr_r=0x1080000\0" \
+        "ramdisk_addr_r=0x3080000\0" \
+        "preloadaddr=0x4000000\0"\
+        "cvbs_drv=0\0"\
+        "osd_reverse=0\0"\
+        "video_reverse=0\0"\
+        "boot_part=boot\0"\
+        "initargs="\
+            "rootfstype=ramfs init=/init console=ttyS0,115200n8 no_console_suspend earlyprintk=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+            "\0"\
+        "switch_bootmode=" \
+            "get_rebootmode;" \
+            "if test ${reboot_mode} = factory_reset; then " \
+                "run boot_recovery;" \
+            "else if test ${reboot_mode} = selfinstall; then " \
+                "oem fdisk;" \
+                "run boot_recovery;" \
+            "else if test ${reboot_mode} = cold_boot; then " \
+                /*"run try_auto_burn; "*/ \
+            "else if test ${reboot_mode} = fastboot; then " \
+                "fastboot;" \
+            "fi;fi;fi;fi;" \
+            "\0" \
+        "boot_recovery="\
+            "hdmitx edid; "\
+            "if test ${hdmimode} = custombuilt; then setenv cmode modeline=${modeline} customwidth=${customwidth} customheight=${customheight}; fi; "\
+            "if test ${hdmimode} == 2160p*; then setenv hdmimode 1080p60hz; fi; "\
+            "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} "\
+                "vout=${hdmimode},enable hdmimode=${hdmimode} ${cmode} voutmode=${voutmode} "\
+                "cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} "\
+                "androidboot.selinux=permissive jtag=disable "\
+                "androidboot.hardware=" CONFIG_DEVICE_PRODUCT " "\
+                "recovery_part=recovery recovery_offset=0; "\
+            "movi read dtbs 0 ${cramfsaddr}; " \
+            "if test " CONFIG_DEVICE_PRODUCT " = odroidn2; then " \
+                "cramfsload ${dtb_mem_addr} meson64_" CONFIG_DEVICE_PRODUCT "_android.dtb;" \
+                "cramfsload ${loadaddr} odroid${variant}-opp.dtbo;" \
+                "fdt addr ${dtb_mem_addr};" \
+                "fdt resize 8192;" \
+                "fdt apply ${loadaddr};" \
+            "else " \
+                "cramfsload ${dtb_mem_addr} meson64_odroid${variant}_android.dtb;" \
+            "fi;" \
+            "movi read recovery 0 ${loadaddr}; " \
+            "booti ${loadaddr} - ${dtb_mem_addr}; " \
+            "bootm ${loadaddr};" \
+        "boot_rawimage=" \
+	    "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} " \
+            "vout=${outputmode},enable cvbsmode=${cvbsmode} " \
+            "hdmimode=${hdmimode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} " \
+            "androidboot.selinux=permissive androidboot.firstboot=${firstboot} jtag=disable " \
+            "androidboot.hardware=" CONFIG_DEVICE_PRODUCT "; " \
+	        "movi read dtbs 0 ${cramfsaddr}; " \
+            "if test " CONFIG_DEVICE_PRODUCT " = odroidn2; then " \
+                "cramfsload ${dtb_mem_addr} meson64_" CONFIG_DEVICE_PRODUCT "_android.dtb;" \
+                "cramfsload ${loadaddr} odroid${variant}-opp.dtbo;" \
+                "fdt addr ${dtb_mem_addr};" \
+                "fdt resize 8192;" \
+                "fdt apply ${loadaddr};" \
+            "else " \
+                "cramfsload ${dtb_mem_addr} meson64_odroid${variant}_android.dtb;" \
+            "fi;" \
+	        "movi read boot 0 ${loadaddr}; " \
+	        "booti ${loadaddr} - ${dtb_mem_addr}; " \
+	        "bootm ${loadaddr}; " \
+        "init_display="\
+            "osd open; osd clear; " \
+            "for n in ${mmc_list}; do " \
+                "if load mmc ${n} ${preloadaddr} logo.bmp.gz; then " \
+                    "setenv logo_addr_r ${loadaddr}; " \
+                    "unzip ${preloadaddr} ${logo_addr_r}; " \
+                    "bmp display ${logo_addr_r}; " \
+                    "bmp scale; " \
+                "elif load mmc ${n} ${preloadaddr} logo.bmp; then " \
+                    "setenv logo_addr_r ${preloadaddr}; " \
+                    "bmp display ${logo_addr_r}; " \
+                    "bmp scale; " \
+                "fi; " \
+            "done; " \
+            "vout output ${outputmode};\0" \
+	"bios_offset_uboot=0x00000000\0" \
+	"bios_sizeof_uboot=0x0f0000\0" \
+	"bios_offset_ubootenv=0x000f0000\0" \
+	"bios_sizeof_ubootenv=0x010000\0" \
+	"bios_offset_dtb=0x00100000\0" \
+	"bios_sizeof_dtb=0x020000\0" \
+	"bios_offset_kernel=0x00120000\0" \
+	"bios_sizeof_kernel=0x3c0000\0" \
+	"bios_offset_initrd=0x004e0000\0" \
+	"bios_sizeof_initrd=0x320000\0" \
+	"spiupdate_uboot="\
+		"sf probe; "\
+		"load mmc 1 ${loadaddr} u-boot.bin; "\
+		"sf update ${loadaddr} ${bios_offset_uboot} ${bios_sizeof_uboot}\0"\
+	"spiupdate_dtb="\
+		"sf probe; "\
+		"load mmc 1 ${loadaddr} meson64_odroidn2_spibios.dtb; "\
+		"sf update ${loadaddr} ${bios_offset_dtb} ${bios_sizeof_dtb}\0"\
+	"spiupdate_kernel="\
+		"sf probe; "\
+		"load mmc 1 ${loadaddr} uImage; "\
+		"sf update ${loadaddr} ${bios_offset_kernel} ${bios_sizeof_kernel}\0"\
+	"spiupdate_initrd="\
+		"sf probe; "\
+		"load mmc 1 ${loadaddr} rootfs.cpio.uboot; "\
+		"sf update ${loadaddr} ${bios_offset_initrd} ${bios_sizeof_initrd}\0"\
+	"spiupdate_full="\
+		"sf probe; "\
+		"load mmc 1 ${preloadaddr} spiboot.img; "\
+		"sf update ${preloadaddr} 0 ${filesize}\0"\
+	"petitboot,interface=eth0\0"\
+	"petitboot,timeout=10\0"\
+	"petitboot,autoboot=true\0"\
+	"petitboot,console=" CONFIG_DEFAULT_CONSOLE \
+	"boot_spi="\
+		"sf probe; "\
+		"sf read ${preloadaddr} ${bios_offset_kernel} ${bios_sizeof_kernel}; "\
+		"sf read ${ramdisk_addr_r} ${bios_offset_initrd} ${bios_sizeof_initrd}; "\
+		"sf read ${fdt_addr_r} ${bios_offset_dtb} ${bios_sizeof_dtb}; "\
+		"if test -e mmc 1:1 petitboot.cfg; then "\
+			"load mmc 1:1 ${loadaddr} petitboot.cfg; "\
+			"ini petitboot; "\
+		"fi; " \
+		"if test -e mmc 1:1 spiboot.img; then " \
+			"fdt addr ${fdt_addr_r}; " \
+			"fdt resize; " \
+			"fdt set /emmc@ffe07000 status 'disabled'; " \
+			"fdt set /soc/cbus/spifc@14000 status 'okay'; " \
+		"fi; " \
+		"hdmitx edid; "\
+		"osd open; osd clear; vout output ${outputmode}; "\
+		"setenv bootargs ${initargs} console=tty0 "\
+			"logo=osd0,loaded,0x3d800000 "\
+			"osd_reverse=0 video_reverse=0 vout=${vout} "\
+			"hdmimode=${hdmimode} voutmode=${voutmode} modeline=${modeline} "\
+			"customwidth=${customwidth} customheight=${customheight} "\
+			"petitboot,write?=true "\
+			"petitboot,autoboot=${petitboot,autoboot} "\
+			"petitboot,bootdevs=${petitboot,bootdevs} "\
+			"petitboot,console=${petitboot,console} "\
+			"petitboot,interface=${petitboot,interface} "\
+			"petitboot,timeout=${petitboot,timeout}; "\
+		"bootm ${preloadaddr} ${ramdisk_addr_r} ${fdt_addr_r};\0"
+
+#endif