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| author | ckkim <changkon12@gmail.com> | 2021-08-31 12:03:25 +0900 |
|---|---|---|
| committer | Dongjin Kim <tobetter@gmail.com> | 2021-12-30 18:51:14 +0900 |
| commit | acd93cf2444c1395dc57eb923e53f354b0e18e6d (patch) | |
| tree | f0acef4b9aed44cceb7b36bd74a7ea0ac2dbec0f | |
| parent | d444cff1e19d7b5e8855d6f0eadae042f3b0bd4b (diff) | |
| download | u-boot-odroid-c1-acd93cf2444c1395dc57eb923e53f354b0e18e6d.tar.gz | |
ODROID-COMMON: drivers/mmc: Add support eMMC H/W reset
If emmc rst_n function is not enabled, must execute this command in the u-boot shell.
=> mmc rst-function 0 1
Signed-off-by: ckkim <changkon12@gmail.com>
Change-Id: I21a6ac376032cc2b7b699c889bc78d8f58301488
| -rw-r--r-- | drivers/mmc/rockchip_sdhci.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index c7071d8165..92873af484 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -37,6 +37,12 @@ DECLARE_GLOBAL_DATA_PTR; #define PHYCTRL_FREQSEL_150M 0x3 /* Rockchip specific Registers */ +#define DWCMSHC_VER_ID 0x500 +#define DWCMSHC_VER_TYPE 0x504 +#define DWCMSHC_HOST_CTRL3 0x508 +#define DWCMSHC_EMMC_CONTROL 0x52c +#define DWCMSHC_EMMC_ATCTRL 0x540 + #define DWCMSHC_EMMC_DLL_CTRL 0x800 #define DWCMSHC_EMMC_DLL_RXCLK 0x804 #define DWCMSHC_EMMC_DLL_TXCLK 0x808 @@ -55,6 +61,8 @@ DECLARE_GLOBAL_DATA_PTR; #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) #define DLL_RXCLK_NO_INVERTER 1 #define DLL_RXCLK_INVERTER 0 +#define DWCMSHC_EMMC_RST_N BIT(2) +#define DWCMSHC_EMMC_RST_N_OE BIT(3) #define DWCMSHC_ENHANCED_STROBE BIT(8) #define DLL_LOCK_WO_TMOUT(x) \ ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ @@ -369,6 +377,24 @@ static int rk3568_emmc_get_phy(struct udevice *dev) return 0; } +static int rk3568_emmc_hw_reset(struct udevice *dev) +{ + struct rockchip_sdhc *prv = dev_get_priv(dev); + struct sdhci_host *host = &prv->host; + u32 extra; + + extra = sdhci_readl(host, DWCMSHC_EMMC_CONTROL); + extra |= DWCMSHC_EMMC_RST_N_OE; + extra &= ~DWCMSHC_EMMC_RST_N; + sdhci_writel(host, extra, DWCMSHC_EMMC_CONTROL); + udelay(20); + + extra |= DWCMSHC_EMMC_RST_N; + sdhci_writel(host, extra, DWCMSHC_EMMC_CONTROL); + udelay(300); + return 0; +} + static int arasan_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) { struct rockchip_sdhc *priv = @@ -455,6 +481,9 @@ static int arasan_sdhci_probe(struct udevice *dev) host->mmc->dev = dev; upriv->mmc = host->mmc; + if (dev_read_bool(dev, "cap-mmc-hw-reset")) + rk3568_emmc_hw_reset(dev); + return sdhci_probe(dev); } |