diff options
-rw-r--r-- | arch/arm/cpu/armv8/g12b/firmware/scp_task/Makefile | 3 | ||||
-rw-r--r-- | board/hardkernel/odroidn2/firmware/scp_task/pwr_ctrl.c | 5 | ||||
-rw-r--r-- | board/hardkernel/odroidn2/firmware/timing.c | 6 |
3 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/g12b/firmware/scp_task/Makefile b/arch/arm/cpu/armv8/g12b/firmware/scp_task/Makefile index 82f31b88bb..0ba7577e3f 100644 --- a/arch/arm/cpu/armv8/g12b/firmware/scp_task/Makefile +++ b/arch/arm/cpu/armv8/g12b/firmware/scp_task/Makefile @@ -48,6 +48,9 @@ DUMP_FLAGS = -D -x ifdef CONFIG_ODROID_COMMON CFLAGS += -DCONFIG_ODROID_COMMON endif +ifdef CONFIG_ODROID_N2L +CFLAGS += -DCONFIG_SYS_LED +endif LDFLAGS=-Bstatic #LDFLAGS+=$(LD_LIB_PATH_ARM:%=-L%) -lm -lc -lgcc diff --git a/board/hardkernel/odroidn2/firmware/scp_task/pwr_ctrl.c b/board/hardkernel/odroidn2/firmware/scp_task/pwr_ctrl.c index a551e19546..a8443b95ba 100644 --- a/board/hardkernel/odroidn2/firmware/scp_task/pwr_ctrl.c +++ b/board/hardkernel/odroidn2/firmware/scp_task/pwr_ctrl.c @@ -74,6 +74,11 @@ static void power_off_at_24M(unsigned int suspend_from) writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N); writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C); } +#ifdef CONFIG_SYS_LED + /*N2-Lite set gpioao_6 low to power off sys_led(red)*/ + writel(readl(AO_GPIO_O) & (~(1 << 6)), AO_GPIO_O); + writel(readl(AO_GPIO_O_EN_N) & (~(1 << 6)), AO_GPIO_O_EN_N); +#endif /*set gpioao_4 low to power off vcck_a*/ writel(readl(AO_GPIO_O) & (~(1 << 4)), AO_GPIO_O); diff --git a/board/hardkernel/odroidn2/firmware/timing.c b/board/hardkernel/odroidn2/firmware/timing.c index 4ac3287257..108db5fd28 100644 --- a/board/hardkernel/odroidn2/firmware/timing.c +++ b/board/hardkernel/odroidn2/firmware/timing.c @@ -424,9 +424,15 @@ bl2_reg_t __bl2_reg[] = { /* Enable 5V_EN */ {GPIO_O_EN_N_REG3, (1 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0}, {GPIO_O_REG3, (1 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0}, +#if defined(CONFIG_ODROID_N2L) + /* Enable CPUA ,control by GPIOAO_4 */ + {AO_GPIO_O_EN_N, (0 << 4) | (0 << 6), (0x5 << 4), 0, BL2_INIT_STAGE_1, 0}, + {AO_GPIO_O, (0x5 << 4), (0x5 << 4), 0, BL2_INIT_STAGE_1, 0}, +#else /* Enable CPUA ,control by GPIOAO_4 */ {AO_GPIO_O_EN_N, (0 << 4), (1 << 4), 0, BL2_INIT_STAGE_1, 0}, {AO_GPIO_O, (1 << 4), (1 << 4), 0, BL2_INIT_STAGE_1, 0}, +#endif /* Enable VCCK */ {AO_SEC_REG0, (1 << 0), (1 << 0), 0, BL2_INIT_STAGE_1, 0}, {AO_GPIO_O, (1 << 31), (1 << 31), 0, BL2_INIT_STAGE_1, 0}, |