diff options
| author | Chin Liang See <clsee@altera.com> | 2014-03-18 20:03:32 -0700 |
|---|---|---|
| committer | Chin Liang See <clsee@altera.com> | 2014-03-18 20:03:32 -0700 |
| commit | 7d2eb72762278fc9f06af2eac22f0c481e044b72 (patch) | |
| tree | dd7af50d29d00aa31a9b0b723e5211018ae08a8b | |
| parent | 5c8d037b139ecc62234aab98c93f7aa5da5a3ddb (diff) | |
| download | u-boot-socfpga-7d2eb72762278fc9f06af2eac22f0c481e044b72.tar.gz | |
FogBugz #188622: Ensure BootROM works if SDMMC PWREN is usedrel_socfpga_v2013.01.01_14.03.02
If SDMMC PWREN is used, we need to ensure BootROM always
reconfigure IOCSR and pinmux after warm reset. This is to cater
the use case of board design which is using SDMMC PWREN pins.
Signed-off-by: Chin Liang See <clsee@altera.com>
| -rw-r--r-- | arch/arm/cpu/armv7/socfpga/spl.c | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/socfpga/system_manager.c | 13 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-socfpga/system_manager.h | 2 |
3 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 07ada05121..3e20342df3 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -531,6 +531,12 @@ void spl_board_init(void) #endif /* CONFIG_PRELOADER_WARMRST_SKIP_CFGIO */ #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ + /* + * If SDMMC PWREN is used, we need to ensure BootROM always reconfigure + * IOCSR and pinmux after warm reset. This is to cater the use case + * of board design which is using SDMMC PWREN pins. + */ + sysmgr_sdmmc_pweren_mux_check(); #ifdef CONFIG_HW_WATCHDOG WATCHDOG_RESET(); diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c index 132bd49afb..e0be67af8b 100644 --- a/arch/arm/cpu/armv7/socfpga/system_manager.c +++ b/arch/arm/cpu/armv7/socfpga/system_manager.c @@ -83,3 +83,16 @@ void sysmgr_pinmux_init(void) writel(reg_value, SYSMGR_FPGAINTF_MODULE); } } + +/* + * If SDMMC PWREN is used, we need to ensure BootROM always reconfigure + * IOCSR and pinmux after warm reset. This is to cater the use case + * of board design which is using SDMMC PWREN pins. + */ +void sysmgr_sdmmc_pweren_mux_check(void) +{ + if (readl(SYSMGR_PINMUXGRP_FLASHIO1) == 3) + writel(SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX | + SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO, + CONFIG_SYSMGR_ROMCODEGRP_CTRL); +} diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h index c7a1e682a2..75482c0e4f 100644 --- a/arch/arm/include/asm/arch-socfpga/system_manager.h +++ b/arch/arm/include/asm/arch-socfpga/system_manager.h @@ -22,6 +22,7 @@ #ifndef __ASSEMBLY__ /* declaration for system_manager.c */ void sysmgr_pinmux_init(void); +void sysmgr_sdmmc_pweren_mux_check(void); /* declaration for handoff table type */ typedef unsigned long sys_mgr_pinmux_entry_t; @@ -65,6 +66,7 @@ extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM]; /* pin mux */ #define SYSMGR_PINMUXGRP (SOCFPGA_SYSMGR_ADDRESS + 0x400) +#define SYSMGR_PINMUXGRP_FLASHIO1 (SYSMGR_PINMUXGRP + 0x54) #define SYSMGR_PINMUXGRP_NANDUSEFPGA (SYSMGR_PINMUXGRP + 0x2F0) #define SYSMGR_PINMUXGRP_EMAC1USEFPGA (SYSMGR_PINMUXGRP + 0x2F8) #define SYSMGR_PINMUXGRP_SDMMCUSEFPGA (SYSMGR_PINMUXGRP + 0x308) |