FogBugz #371464-2: Adding function to decide PLL ramp is required

Adding function to decide whether PLL ramping is required. PLL ramp
will ensure both MPU clock and NOC clock are increased in small
increment steps which started from a safe threshold value. The PLL
ramp is only required when the intended final MPU clock and NOC clock
is above the safe threshold value.

Signed-off-by: Chin Liang See <clsee@altera.com>

2 files changed, 71 insertions, 0 deletions

diff --git a/arch/arm/cpu/armv7/socfpga_arria10/clock_manager.c b/arch/arm/cpu/armv7/socfpga_arria10/clock_manager.c
index d782bcc1d0..4426742adb 100755
--- a/arch/arm/cpu/armv7/socfpga_arria10/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga_arria10/clock_manager.c
@@ -511,6 +511,71 @@ static u32 cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg,
 	clk_hz /= (main_cfg->nocclk_cnt + 1);
 	return clk_hz;
 }
+
+/* return 1 if PLL ramp is required */
+static int cm_is_pll_ramp_required(int main0periph1,
+				   struct mainpll_cfg *main_cfg,
+				   struct perpll_cfg *per_cfg)
+{
+
+	/* Check for main PLL */
+	if (main0periph1 == 0) {
+		/*
+		 * PLL ramp is not required if both MPU clock and NOC clock are
+		 * not sourced from main PLL
+		 */
+		if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
+		    main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN)
+			return 0;
+
+		/*
+		 * PLL ramp is required if MPU clock is sourced from main PLL
+		 * and MPU clock is over 900MHz (as advised by HW team)
+		 */
+		if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
+		    (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
+		     CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
+			return 1;
+
+		/*
+		 * PLL ramp is required if NOC clock is sourced from main PLL
+		 * and NOC clock is over 300MHz (as advised by HW team)
+		 */
+		if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN &&
+		    (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
+		     CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
+			return 1;
+
+	} else if (main0periph1 == 1) {
+		/*
+		 * PLL ramp is not required if both MPU clock and NOC clock are
+		 * not sourced from periph PLL
+		 */
+		if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
+		    main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI)
+			return 0;
+
+		/*
+		 * PLL ramp is required if MPU clock are source from periph PLL
+		 * and MPU clock is over 900MHz (as advised by HW team)
+		 */
+		if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
+		    (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
+		     CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
+			return 1;
+
+		/*
+		 * PLL ramp is required if NOC clock are source from periph PLL
+		 * and NOC clock is over 300MHz (as advised by HW team)
+		 */
+		if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI &&
+		    (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
+		     CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
+			return 1;
+	}
+	return 0;
+}
+
 /*
  * Setup clocks while making no assumptions of the
  * previous state of the clocks.
diff --git a/arch/arm/include/asm/arch-socfpga_arria10/clock_manager.h b/arch/arm/include/asm/arch-socfpga_arria10/clock_manager.h
index fc32d4e2dd..cb25a61f9f 100755
--- a/arch/arm/include/asm/arch-socfpga_arria10/clock_manager.h
+++ b/arch/arm/include/asm/arch-socfpga_arria10/clock_manager.h
@@ -188,4 +188,10 @@ extern uint32_t cm_l4_sys_free_clk_hz;
 #define CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB	27
 #define CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB	28
 
+/* PLL ramping work around */
+#define CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ	900000000
+#define CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ	300000000
+#define CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ	100000000
+#define CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ	 33000000
+
 #endif /* _SOCFPGA_CLOCK_MANAGER_H_ */