FogBugz #206562-1: Removes the dwc usb driver

This commit removes the dwc usb driver in place of the community dwc2 USB
driver.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>

5 files changed, 1 insertions, 995 deletions

diff --git a/Makefile b/Makefile
index c62358bb71..c41f851078 100644
--- a/Makefile
+++ b/Makefile
@@ -326,7 +326,6 @@ LIBS-y += drivers/usb/musb/libusb_musb.o
 LIBS-y += drivers/usb/musb-new/libusb_musb-new.o
 LIBS-y += drivers/usb/phy/libusb_phy.o
 LIBS-y += drivers/usb/ulpi/libusb_ulpi.o
-LIBS-y += drivers/usb/dwc_otg/libusb_dwc.o
 LIBS-y += drivers/video/libvideo.o
 LIBS-y += drivers/watchdog/libwatchdog.o
 LIBS-y += common/libcommon.o
diff --git a/drivers/usb/dwc_otg/Makefile b/drivers/usb/dwc_otg/Makefile
deleted file mode 100644
index 14d40f1885..0000000000
--- a/drivers/usb/dwc_otg/Makefile
+++ /dev/null
@@ -1,46 +0,0 @@
-#
-# (C) Copyright 2000-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libusb_dwc.o
-
-COBJS-$(CONFIG_USB_DWC_OTG_HCD) += dwc_usb.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/drivers/usb/dwc_otg/dwc_usb.c b/drivers/usb/dwc_otg/dwc_usb.c
deleted file mode 100644
index de33ef778d..0000000000
--- a/drivers/usb/dwc_otg/dwc_usb.c
+++ /dev/null
@@ -1,942 +0,0 @@
-/*
- * Copyright (C) 2012
- * Altera Corporation <www.altera.com>
- * Created with references to Linux dwc usb driver
- *
- * Author: Tien Hock Loh <thloh@altera.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA  02111-1307  USA
- */
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <common.h>
-
-#include <usb.h>
-#include <usb_defs.h>
-
-#define usb_base			CONFIG_SYS_USB_ADDRESS
-
-#define MAX_PACKET_SIZE			1023
-#define DATA0				0
-#define DATA1				2
-#define DATASETUP			3
-
-/* MSC control transfers */
-#define USB_MSC_BBB_RESET		0xFF
-#define USB_MSC_BBB_GET_MAX_LUN		0xFE
-
-#define CONFIG_DWC_USB_NPTXFDEP		512
-#define CONFIG_DWC_USB_NPTXFSTADDR	512
-#define CONFIG_DWC_USB_RXFDEP		512
-#define CONFIG_DWC_USB_HPTXFSIZ		512
-
-#define DWC_USBCFG_ULPI_EXT_VBUS_DRV	1
-
-#define	DWC_GINTSTS			0x014
-#define DWC_GINTSTS_CURMOD		(1<<0)
-#define DWC_GINTSTS_CONIDSTSCHNG	(1<<28)
-#define DWC_GINTSTS_RXFLVL		(1<<4)
-#define DWC_GINTSTS_SOF			(1<<3)
-#define DWC_GINTSTS_USBRESET		(1<<12)
-#define DWC_GINTSTS_PRTINT		(1<<24)
-
-#define	DWC_GOTGCTL			0x000
-#define DWC_GOTGCTL_CONIDSTS		(1<<16)
-#define DWC_GOTGCTL_HSTNEGSCS		(1<<8)
-#define DWC_GOTGCTL_HNPREQ		(1<<9)
-#define DWC_GOTGCTL_DEVHNPEN		(1<<11)
-
-#define	DWC_GINTMSK			0x018
-#define DWC_GINTMSK_SOF			(1<<3)
-#define DWC_GINTMSK_PRTINTMSK		(1<<24)
-#define DWC_GINTMSK_ENUMDONE		(1<<13)
-#define DWC_GINTMSK_EARLYSUSP		(1<<10)
-#define DWC_GINTMSK_USBSUSP		(1<<11)
-#define DWC_GINTMSK_SOFINTR		(1<<3)
-#define DWC_GINTMSK_NPTXEMPMSK		(1<<5)
-#define DWC_GINTMSK_RXFLVL		(1<<4)
-#define DWC_GINTMSK_OTGINTR		(1<<2)
-#define DWC_GINTMSK_MODEMIS		(1<<1)
-#define DWC_GINTMSK_USBRESET		(1<<12)
-
-#define DWC_HPRT			0x0440
-#define DWC_HPRT_PRTPWR			(1<<12)
-#define DWC_HPRT_PRTRST			(1<<8)
-#define DWC_HPRT_PRTENA			(1<<2)
-#define DWC_HPRT_PRTDET			(1<<1)
-#define DWC_HPRT_PRTENCHNG		(1<<3)
-#define DWC_HPRT_PRTSPD			(1<<17)
-#define DWC_HPRT_PRTSPD_MSK		(3<<17)
-#define DWC_HPRT_PRTSPD_HS		(0<<17)
-#define DWC_HPRT_PRTSPD_FS		(1<<17)
-#define DWC_HPRT_PRTSPD_LS		(2<<17)
-#define DWC_HPRT_FSLSUPP		(1<<2)
-#define DWC_HPRT_PRTCONNSTS		(1<<0)
-
-#define DWC_HCTSIZN(x)			(0x510+0x20*x)
-#define DWC_HCTSIZN_PKTCNT(c)		(c << 19)
-#define DWC_HCTSIZN_XFERSIZE(x)		(x << 0)
-#define DWC_HCTSIZN_PID(x)		(x << 29)
-#define DWC_HCTSIZN_PID_READ		(3 << 29)
-#define DWC_HCTSIZN_PING		(1 << 31)
-
-#define DWC_HCINT(x)			(0x508+0x20*x)
-#define DWC_HCINTMSK			0x50C
-#define DWC_HCINT_XFERCOMP		(1<<0)
-#define DWC_HCINT_CHHLTD		(1<<1)
-#define DWC_HCINT_NAK			(1<<4)
-#define DWC_HCINT_ACK			(1<<5)
-
-#define DWC_HCCHAR			(0x500)
-#define DWC_HCCHARN(x)			(0x500+0x20*x)
-#define DWC_HCCHARN_CHENA		(1 << 31)
-#define DWC_HCCHARN_CHDIS		(1 << 30)
-#define DWC_HCCHARN_EPDIR		(1 << 15)
-#define DWC_HCCHARN_EPNUM(x)		(x << 11)
-#define DWC_HCCHARN_MPS(x)		(x << 0)
-#define DWC_HCCHARN_LSPDDEV(x)		(x<<17)
-#define DWC_HCCHARN_EPTYPE(x)		(x<<18)
-#define DWC_HCCHARN_MC(x)		(x<<20)
-#define DWC_HCCHARN_DEVADDR(x)		(x<<22)
-
-#define DWC_GAHBCFG			(0x8)
-#define DWC_GAHBCFG_BURSTLEN(x)		(x<<1)
-#define DWC_GAHBCFG_GLBLINTRMSK		(1<<0)
-#define DWC_GAHBCFG_NPTXFEMPLVL		0x111
-#define DWC_GAHBCFG_PTXFEMPLVL		0x111
-#define DWC_GAHBCFG_DMAEN		(1<<5)
-
-#define	DWC_GRXSTSP			0x020
-#define DWC_GRXSTSP_PKTSTS(x)		(x<<17)
-
-#define GNPTXFSIZ_NPTXFDEP(x)		(x<<16)
-
-#define	DWC_GOTGINT			0x004
-#define DWC_GOTGINT_DBNCEDONE		(1<<19)
-
-#define DWC_DAINT		0x818
-#define DWC_DEACHINT		0x838
-#define DWC_DIEPINT(x)		(0x908+x*0x20)
-#define DWC_DOEPINT(x)		(0xb08+x*0x20)
-
-/* general bits */
-#define DWC_GLBINTRMASK				0x0001
-#define DWC_DMAENABLE				0x0020
-#define DWC_NPTXEMPTYLVL_EMPTY			0x0080
-#define DWC_NPTXEMPTYLVL_HALFEMPTY		0x0000
-#define DWC_PTXEMPTYLVL_EMPTY			0x0100
-#define DWC_PTXEMPTYLVL_HALFEMPTY		0x0000
-
-#define DWC_SLAVE_ONLY_ARCH			0
-#define DWC_EXT_DMA_ARCH			1
-#define DWC_INT_DMA_ARCH			2
-
-#define DWC_MODE_HNP_SRP_CAPABLE		0
-#define DWC_MODE_SRP_ONLY_CAPABLE		1
-
-#define DWC_MODE_NO_HNP_SRP_CAPABLE		2
-#define DWC_MODE_SRP_CAPABLE_DEVICE		3
-#define DWC_MODE_NO_SRP_CAPABLE_DEVICE		4
-#define DWC_MODE_SRP_CAPABLE_HOST		5
-#define DWC_MODE_NO_SRP_CAPABLE_HOST		6
-
-/*
- * The Host Global Registers structure defines the size and relative field
- * offsets for the Host Mode Global Registers.  Host Global Registers offsets
- * 400h-7FFh.
-*/
-#define DWC_HCFG	0x400
-#define DWC_HFIR	0x404
-#define DWC_HFNUM	0x408
-#define DWC_HPTXSTS	0x410
-#define DWC_HAINT	0x414
-#define DWC_HAINTMSK	0x418
-
-/*
- * Host Channel Specific Registers. 500h-5FCh
- */
-
-#define DWC_HCSPLT	0x504
-#define DWC_HCTSIZ	0x510
-#define DWC_HCDMA	0x514
-
-#define	DWC_GUSBCFG	0x00C
-#define	DWC_GRSTCTL	0x010
-
-
-#define	DWC_GRXSTSR	0x01C
-#define	DWC_GRXFSIZ	0x024
-
-#define	DWC_GNPTXSTS	0x02C
-#define	DWC_GI2CCTL	0x030
-#define	DWC_VDCTL	0x034
-#define	DWC_GGPIO	0x038
-#define	DWC_GUID	0x03C
-#define	DWC_GSNPSID	0x040
-#define	DWC_GHWCFG1	0x044
-#define	DWC_GHWCFG2	0x048
-#define	DWC_GHWCFG3	0x04c
-#define	DWC_GHWCFG4	0x050
-#define	DWC_HPTXFSIZ	0x100
-#define	DWC_DPTX_FSIZ_DIPTXF(x)	(0x104 + x * 4)	/* 15 <= x > 1 */
-
-
-#define DWC_GLBINTRMASK			0x0001
-#define DWC_DMAENABLE			0x0020
-#define DWC_NPTXEMPTYLVL_EMPTY		0x0080
-#define DWC_NPTXEMPTYLVL_HALFEMPTY	0x0000
-#define DWC_PTXEMPTYLVL_EMPTY		0x0100
-#define DWC_PTXEMPTYLVL_HALFEMPTY	0x0000
-
-#define DWC_SLAVE_ONLY_ARCH		0
-#define DWC_EXT_DMA_ARCH		1
-#define DWC_INT_DMA_ARCH		2
-
-#define DWC_MODE_HNP_SRP_CAPABLE	0
-#define DWC_MODE_SRP_ONLY_CAPABLE	1
-#define DWC_MODE_NO_HNP_SRP_CAPABLE	2
-#define DWC_MODE_SRP_CAPABLE_DEVICE	3
-#define DWC_MODE_NO_SRP_CAPABLE_DEVICE	4
-#define DWC_MODE_SRP_CAPABLE_HOST	5
-#define DWC_MODE_NO_SRP_CAPABLE_HOST	6
-
-/*
- * The Host Global Registers structure defines the size and relative field
- * offsets for the Host Mode Global Registers.  Host Global Registers offsets
- * 400h-7FFh.
-*/
-#define DWC_HCFG	0x400
-#define DWC_HFIR	0x404
-#define DWC_HFNUM	0x408
-#define DWC_HPTXSTS	0x410
-#define DWC_HAINT	0x414
-#define DWC_HAINTMSK	0x418
-
-#define DWC_HCSPLT	 0x504
-#define DWC_HCTSIZ	 0x510
-#define DWC_HCDMA	 0x514
-
-#define HCSPLT_SPLT_ENABLE(x) 0x0504
-
-#define DWC_GUSBCFG_PHYIF		(1<<3)
-#define DWC_GUSBCFG_ULPI_UTIM_SEL	(1<<4)
-#define DWC_GUSBCFG_PHYSEL		(1<<6)
-#define DWC_GUSBCFG_SRPCAP		(1<<8)
-#define DWC_GUSBCFG_HNPCAP		(1<<9)
-#define DWC_GUSBCFG_FORCEHSTMODE	(1<<29)
-
-#define DWC_GRXFSIX_RXFDEP(x) 1
-#define	DWC_GNPTXFSIZ		0x028
-#define DWC_GNPTXFSIZ_NPTXFDEP(x) 1
-#define DWC_GNPTXFSIZ_NPTXSTADDR(x) 1
-
-#define FIFO(channel) 0x1000*(channel+1)
-
-struct core_init {
-	int dma;
-	int usb;
-	int hnp_capable;
-	int srp_capable;
-	int fs;
-};
-
-struct hwcfg {
-	int perio_tx_fifo_size[16];
-	int tx_fifo_size[16];
-	int num_in_eps;
-	int num_out_eps;
-
-} hwcfg;
-
-int dwc_wait_xfer_complete(int channel)
-{
-	unsigned int start;
-	const unsigned int timeout = 10000000;
-
-	/* wait for xfer complete */
-	start = get_timer(0);
-	while (get_timer(start) < timeout) {
-		if ((__raw_readl(usb_base + DWC_HCINT(channel))
-				& (DWC_HCINT_XFERCOMP)))
-			return 0;
-	}
-
-	return -1;
-}
-
-int wait_for_connection(void)
-{
-	unsigned int start;
-	const unsigned int timeout = 10000;
-
-	setbits_le32(usb_base + DWC_GINTMSK, DWC_GINTMSK_PRTINTMSK);
-	clrbits_le32(usb_base + DWC_HCFG, DWC_HPRT_FSLSUPP);
-
-	__raw_writel(DWC_GAHBCFG_GLBLINTRMSK, usb_base + DWC_GAHBCFG);
-
-	setbits_le32(usb_base + DWC_HPRT, DWC_HPRT_PRTPWR);
-
-	/*
-	 * ensure core is in A-host mode and connected
-	 * we'll have to loop a couple of times, and wait a little
-	 * so that prtpwr gets its time to init
-	 */
-	start = get_timer(0);
-	do {
-		if (get_timer(start) > timeout)
-			return -1;
-	} while (!(__raw_readl(usb_base + DWC_HPRT) & DWC_HPRT_PRTDET));
-
-	if ((__raw_readl(usb_base + DWC_GINTSTS) & DWC_GINTSTS_CURMOD) != 1)
-		return -1;
-
-	/* clears the port connected interrupt */
-	__raw_writel(__raw_readl(usb_base + DWC_HPRT) | DWC_HPRT_PRTDET,
-		usb_base + DWC_HPRT);
-
-	return 0;
-}
-
-int port_reset(void)
-{
-	setbits_le32(usb_base + DWC_HPRT, DWC_HPRT_PRTRST);
-	{
-		/*
-		 * wait for minimum of 10ms for the reset complete
-		 * wait 15ms instead, just to be sure
-		 */
-		udelay(15000);
-	}
-	clrbits_le32(usb_base + DWC_HPRT, DWC_HPRT_PRTRST);
-	return 0;
-}
-
-int wait_for_debounce(void)
-{
-	/* if not hnp and srp capable, just return 0 */
-	return 0;
-}
-
-int port_enabled(void)
-{
-	while (!(__raw_readl(usb_base + DWC_HPRT) & DWC_HPRT_PRTENCHNG))
-		udelay(100);
-	return 0;
-}
-
-int port_speed(u32 speed)
-{
-	while (!(__raw_readl(usb_base + DWC_GINTSTS) & DWC_GINTSTS_PRTINT))
-		udelay(100);
-	return 0;
-}
-
-int dyn_fifo_config(void)
-{
-	__raw_writel(CONFIG_DWC_USB_RXFDEP,
-			usb_base + DWC_GRXFSIZ);
-	__raw_writel(CONFIG_DWC_USB_NPTXFDEP,
-			usb_base + DWC_GNPTXFSIZ);
-	__raw_writel(CONFIG_DWC_USB_HPTXFSIZ,
-			usb_base + DWC_HPTXFSIZ);
-	return 0;
-}
-
-int switch_to_host(void)
-{
-	setbits_le32(usb_base + DWC_GUSBCFG, DWC_GUSBCFG_FORCEHSTMODE);
-	udelay(25000); /* 25ms delay until the USB switches to host mode */
-
-	if ((__raw_readl(usb_base + DWC_GINTSTS) & DWC_GINTSTS_CURMOD) != 1)
-		return -1;
-
-	return 0;
-}
-
-int dwc_host_init(void)
-{
-	if (switch_to_host())
-		return 1<<1;
-	if (wait_for_connection())
-		return 1<<2;
-	if (port_reset())
-		return 1<<3;
-	if (port_enabled())
-		return 1<<4;
-	if (port_speed(DWC_HPRT_PRTSPD_HS))
-		return 1<<5;
-	if (dyn_fifo_config())
-		return 1<<6;
-	if (wait_for_debounce())
-		return 1<<7;
-	return 0;
-}
-
-void dwc_core_init(struct core_init init)
-{
-	if (init.dma)
-		setbits_le32(usb_base + DWC_GAHBCFG, DWC_GAHBCFG_DMAEN);
-	else
-		clrbits_le32(usb_base + DWC_GAHBCFG, DWC_GAHBCFG_DMAEN);
-	setbits_le32(usb_base + DWC_GAHBCFG,
-		DWC_GAHBCFG_BURSTLEN(0) | DWC_GAHBCFG_GLBLINTRMSK);
-
-	/*
-	 * Configuring the txfifo, only in slave mode we need this interrupt
-	 * don't really need this, since we're not using interrupt
-	 */
-	if (!init.dma)
-		setbits_le32(usb_base + DWC_GAHBCFG,
-			DWC_GAHBCFG_NPTXFEMPLVL | DWC_GAHBCFG_PTXFEMPLVL);
-
-	clrbits_le32(usb_base + DWC_GINTMSK, DWC_GINTMSK_RXFLVL);
-
-	u32 gusbcfg = __raw_readl(usb_base + DWC_GUSBCFG);
-	gusbcfg = init.hnp_capable ? gusbcfg | DWC_GUSBCFG_HNPCAP
-			: gusbcfg & ~(DWC_GUSBCFG_HNPCAP);
-	gusbcfg = init.srp_capable ? gusbcfg | DWC_GUSBCFG_SRPCAP
-			: gusbcfg & ~(DWC_GUSBCFG_SRPCAP);
-	gusbcfg &= ~DWC_GUSBCFG_PHYSEL;
-	gusbcfg |= DWC_GUSBCFG_ULPI_UTIM_SEL;
-	gusbcfg &= ~DWC_GUSBCFG_PHYIF;
-	__raw_writel(gusbcfg, usb_base + DWC_GUSBCFG);
-
-	setbits_le32(usb_base + DWC_GINTMSK,
-		DWC_GINTMSK_OTGINTR | DWC_GINTMSK_MODEMIS);
-
-}
-
-enum ep_type {
-	EP_CTRL = 0,
-	EP_ISOC = 1,
-	EP_BULK = 2,
-	EP_INTR = 3,
-};
-
-struct packet {
-	int channel;
-	int endpoint;
-	int packet_count;
-	int xfer_size;
-	int ep_is_in;
-	int devaddr;
-	enum ep_type type;
-	int mps;
-	int pid;
-};
-
-int dwc_setup_transfer(struct packet p)
-{
-	u32 hctsizn = 0x0;
-	u32 hccharn = 0x0;
-	u32 haintmsk = 0x0;
-	u32 hcintmsk = 0x0;
-
-	haintmsk = __raw_readl(usb_base + DWC_HAINTMSK) | (1 << p.channel);
-	__raw_writel(haintmsk, usb_base + DWC_HAINTMSK);
-
-	hcintmsk = __raw_readl(usb_base + DWC_HCINTMSK) | DWC_HCINT_XFERCOMP;
-	__raw_writel(hcintmsk, usb_base + DWC_HCINTMSK);
-
-	hctsizn |= DWC_HCTSIZN_PKTCNT(p.packet_count);
-	hctsizn |= DWC_HCTSIZN_XFERSIZE(p.xfer_size);
-	hctsizn |= DWC_HCTSIZN_PID(p.pid);
-	__raw_writel(hctsizn, usb_base + DWC_HCTSIZN(p.channel));
-
-	hccharn = p.ep_is_in ? hccharn | DWC_HCCHARN_EPDIR
-				: hccharn & ~DWC_HCCHARN_EPDIR;
-	hccharn |= DWC_HCCHARN_DEVADDR(p.devaddr);
-	hccharn |= DWC_HCCHARN_EPTYPE(p.type);
-	hccharn |= DWC_HCCHARN_EPNUM(p.endpoint);
-	hccharn |= DWC_HCCHARN_MPS(p.mps);
-	hccharn |= 1<<20;
-	hccharn |= DWC_HCCHARN_CHENA;
-	hccharn &= ~DWC_HCCHARN_CHDIS;
-	__raw_writel(hccharn, usb_base + DWC_HCCHARN(p.channel));
-
-	return 0;
-}
-
-static int dwc_read_packet(struct packet p, void *odata)
-{
-	u8 *data = (u8 *)odata;
-	/* clear the xfer complete interrupt */
-	__raw_writel(DWC_HCINT_XFERCOMP, usb_base + DWC_HCINT(p.channel));
-
-	setbits_le32(usb_base + DWC_GINTMSK, DWC_GINTSTS_RXFLVL);
-	/* wait for rxfifo non empty */
-	while (!(__raw_readl(usb_base + DWC_GINTSTS) & DWC_GINTSTS_RXFLVL)) {
-		u32 hccharn = (__raw_readl(usb_base + DWC_HCCHARN(p.channel)) |
-				DWC_HCCHARN_CHENA) & ~DWC_HCCHARN_CHDIS;
-		__raw_writel(hccharn, usb_base + DWC_HCCHARN(p.channel));
-	}
-
-	int read_total = 0;
-
-	int packet_read = 0;
-
-	/* masking rxfifo not empty interrupt */
-	setbits_le32(usb_base + DWC_GINTMSK, DWC_GINTSTS_RXFLVL);
-	__raw_writel(__raw_readl(usb_base + DWC_GINTMSK) | DWC_GINTSTS_RXFLVL,
-			usb_base + DWC_GINTMSK);
-	while (1) {
-		u32 packet_status = __raw_readl(usb_base + DWC_GRXSTSP);
-		if ((packet_status & DWC_GRXSTSP_PKTSTS(0xF)) ==
-			DWC_GRXSTSP_PKTSTS(3)) {
-			break;
-		}
-		if ((packet_status & DWC_GRXSTSP_PKTSTS(0xF)) ==
-			DWC_GRXSTSP_PKTSTS(2)) {
-			int bytecount = ((packet_status >> 4) & (0x7FF));
-
-			packet_read++;
-			read_total += bytecount;
-
-			while (bytecount > 0) {
-				u32 read = __raw_readl(usb_base +
-						FIFO(p.channel));
-				if (bytecount--)
-					*data++ = read & 0xff;
-				if (bytecount--)
-					*data++ = (read & (0xff << 8)) >> 8;
-				if (bytecount--)
-					*data++ = (read & (0xff << 16)) >> 16;
-				if (bytecount--)
-					*data++ = (read & (0xff << 24)) >> 24;
-			}
-
-		}
-		/* re-enable the channel if pktcnt is > 0 */
-		if (packet_read < p.packet_count) {
-			setbits_le32(usb_base + DWC_HCCHARN(p.channel),
-				DWC_HCCHARN_CHENA);
-		}
-	}
-
-
-	/* wait for xfer complete interrupt. */
-	if (dwc_wait_xfer_complete(p.channel))
-		printf("DW_USB: Timed out waiting for xfer complete interrupt");
-
-	/* clear the xfer complete interrupt */
-	__raw_writel(DWC_HCINT_XFERCOMP, usb_base + DWC_HCINT(p.channel));
-
-	return read_total;
-}
-
-static int dwc_send_packet(struct packet p, u32 *data, int datasize)
-{
-	int i = 0;
-	unsigned int start;
-	const unsigned int timeout = 1000;
-	/* clear xfer complete interrupt. */
-	__raw_writel(DWC_HCINT_XFERCOMP, usb_base + DWC_HCINT(p.channel));
-	for (; i < datasize; i++)
-		__raw_writel(data[i], usb_base + FIFO(p.channel));
-
-	start = get_timer(0);
-	while (get_timer(start) < timeout) {
-		if (__raw_readl(usb_base + DWC_HCINT(p.channel)) &
-			(DWC_HCINT_XFERCOMP))
-			break;
-		if (__raw_readl(usb_base + DWC_HCINT(p.channel)) &
-			(DWC_HCINT_NAK)) {
-			__raw_writel(DWC_HCINT_NAK,
-				usb_base + DWC_HCINT(p.channel));
-			__raw_writel(
-				(__raw_readl(usb_base + DWC_HCCHARN(p.channel)))
-				| (DWC_HCCHARN_CHDIS & ~DWC_HCCHARN_CHENA),
-				usb_base + DWC_HCCHARN(p.channel));
-
-			u32 hcint = __raw_readl(usb_base +
-						DWC_HCINT(p.channel));
-			while (!(hcint & (DWC_HCINT_CHHLTD))) {
-				hcint = __raw_readl(usb_base +
-						DWC_HCINT(p.channel));
-				if (__raw_readl(usb_base + DWC_GINTSTS)
-					& DWC_GINTSTS_RXFLVL) {
-					__raw_readl(usb_base + DWC_GRXSTSP);
-				}
-			}
-			__raw_writel(DWC_HCINT_CHHLTD,
-				usb_base + DWC_HCINT(p.channel));
-			return -1;
-		}
-	}
-
-	if (!(__raw_readl(usb_base + DWC_HCINT(p.channel)) &
-		(DWC_HCINT_XFERCOMP)))
-		printf("DW_USB: Transfer completion interrupt timeout\n");
-
-	/* disables the xfer complete interrupt */
-	setbits_le32(usb_base + DWC_HCINT(p.channel), DWC_HCINT_XFERCOMP);
-
-	start = get_timer(0);
-	while ((__raw_readl(usb_base + DWC_HCCHARN(p.channel))
-		& DWC_HCCHARN_CHENA)) {
-		if (get_timer(start) > timeout) {
-			printf("Timed out waiting for channel to disable\n");
-			return -1;
-		}
-	}
-
-	return 0;
-}
-
-int usb_lowlevel_init(int index, void **controller)
-{
-	struct core_init init;
-	init.dma = 0;
-	init.hnp_capable = 0;
-	init.srp_capable = 0;
-	init.fs = 0;
-	dwc_core_init(init);
-
-	if (dwc_host_init() != 0)
-		return -1;
-
-	return 0;
-}
-
-int usb_lowlevel_stop(int index)
-{
-	clrbits_le32(usb_base + DWC_HPRT, DWC_HPRT_PRTPWR);
-	return 0;
-}
-
-
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
-			void *buffer, int transfer_len)
-{
-	int dir_out = usb_pipeout(pipe);
-	int ep = usb_pipeendpoint(pipe);
-	int total_read = 0;
-	int sent = 0;
-	unsigned int start;
-	const unsigned int timeout = 1000;
-
-	struct packet bulk_msg;
-	bulk_msg.channel = 3;
-	bulk_msg.endpoint = ep;
-	bulk_msg.packet_count = (transfer_len-1) / 512 + 1;
-	bulk_msg.xfer_size = transfer_len;
-	bulk_msg.ep_is_in = !dir_out;
-	bulk_msg.devaddr = usb_pipedevice(pipe);
-	bulk_msg.type = EP_BULK;
-	bulk_msg.mps = MAX_PACKET_SIZE;
-	bulk_msg.pid =
-		usb_gettoggle(dev, ep, dir_out) == DATA0 ? DATA0 : DATA1;
-
-
-	if (dir_out) {
-		__raw_writel(DWC_HCINT_ACK | DWC_HCINT_NAK,
-			usb_base + DWC_HCINT(bulk_msg.channel));
-
-		start = get_timer(0);
-		while (get_timer(start) < timeout && !sent) {
-			dwc_setup_transfer(bulk_msg);
-			if (dwc_send_packet(bulk_msg, buffer, transfer_len/4+1)
-				== 0)
-				sent = 1;
-		}
-		if (!sent)
-			return -1;
-
-		usb_dotoggle(dev, ep, dir_out);
-	}
-	else {
-		while (total_read < transfer_len) {
-			bulk_msg.pid =
-				usb_gettoggle(dev, ep, dir_out) == DATA0 ?
-					DATA0 : DATA1;
-
-			__raw_writel(DWC_HCINT_ACK | DWC_HCINT_NAK,
-				usb_base + DWC_HCINT(bulk_msg.channel));
-
-			dwc_setup_transfer(bulk_msg);
-			total_read += dwc_read_packet(bulk_msg,
-				buffer + total_read);
-
-			/* halt the channel */
-			setbits_le32(usb_base + DWC_HCCHARN(bulk_msg.channel),
-				DWC_HCCHARN_CHDIS | DWC_HCCHARN_CHENA);
-
-			u32 hcint = __raw_readl(
-				usb_base + DWC_HCINT(bulk_msg.channel));
-			while (!(hcint & (DWC_HCINT_CHHLTD))) {
-				hcint = __raw_readl(
-					usb_base + DWC_HCINT(bulk_msg.channel));
-
-			if (__raw_readl(usb_base + DWC_GINTSTS)
-					& DWC_GINTSTS_RXFLVL)
-				__raw_readl(usb_base + DWC_GRXSTSP);
-			}
-
-			__raw_writel(DWC_HCINT_CHHLTD,
-				usb_base + DWC_HCINT(bulk_msg.channel));
-			usb_dotoggle(dev, ep, dir_out);
-		}
-	}
-
-	/* bulk transfer is complete */
-	dev->status = 0;
-	dev->act_len = transfer_len;
-
-	return 0;
-}
-
-static int ctrlreq_setup_phase(struct usb_device *dev,
-				struct devrequest *setup, unsigned long pipe) {
-	struct packet control_msg;
-	int ret = 0;
-
-	control_msg.channel = 0;
-	control_msg.endpoint = 0;
-	control_msg.packet_count = 1;
-	control_msg.xfer_size = sizeof(struct devrequest);
-	control_msg.ep_is_in = 0;
-	control_msg.devaddr = usb_pipedevice(pipe);
-	control_msg.type = EP_CTRL;
-	control_msg.mps = MAX_PACKET_SIZE;
-	control_msg.pid = DATASETUP;
-
-	/* clear xfer complete interrupt. */
-	__raw_writel(DWC_HCINT_XFERCOMP,
-		usb_base + DWC_HCINT(control_msg.channel));
-	__raw_writel(DWC_HCINT_NAK | DWC_HCINT_ACK,
-		usb_base + DWC_HCINT(control_msg.channel));
-
-	dwc_setup_transfer(control_msg);
-
-	ret = dwc_send_packet(control_msg, (void *)setup,
-		sizeof(struct devrequest)/4);
-
-	__raw_writel(DWC_HCINT_XFERCOMP,
-		usb_base + DWC_HCINT(control_msg.channel));
-
-	return ret;
-}
-
-static int ctrlreq_out_data_phase(struct usb_device *dev, unsigned long pipe,
-			int len, void *buffer) {
-	usb_settoggle(dev, usb_pipeendpoint(pipe), 1, 0);
-	int result;
-	int devnum = usb_pipedevice(pipe);
-	int epnum = usb_pipeendpoint(pipe);
-	int txlen = 0;
-	int nextlen = 0;
-	u8 maxpktsize = (1<<dev->maxpacketsize) * 8;
-	int packet_count = len / maxpktsize + 1;
-
-	struct packet control_msg;
-	while (txlen < len) {
-
-		nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen);
-
-		control_msg.channel = 0;
-		control_msg.endpoint = epnum;
-		control_msg.packet_count = packet_count;
-		control_msg.xfer_size = nextlen;
-		control_msg.ep_is_in = 0;
-		control_msg.devaddr = devnum;
-		control_msg.type = EP_CTRL;
-		control_msg.mps = 3;
-		control_msg.pid = DATA1;
-
-		result = dwc_send_packet(control_msg, buffer, txlen);
-
-		if (result != 0)
-			break;
-
-		txlen += nextlen;
-		dev->act_len = txlen;
-	}
-
-	return result;
-}
-
-static int ctrlreq_in_status_phase(struct usb_device *dev, unsigned long pipe)
-{
-	u32 tmp[10];
-	struct packet control_msg;
-
-	usb_settoggle(dev, usb_pipeendpoint(pipe), 1, 0);
-
-	control_msg.channel = 0;
-	control_msg.endpoint = 0;
-	control_msg.packet_count = 1;
-	control_msg.xfer_size = 0;
-	control_msg.ep_is_in = 1;
-	control_msg.devaddr = usb_pipedevice(pipe);
-	control_msg.type = EP_CTRL;
-	control_msg.mps = MAX_PACKET_SIZE;
-	control_msg.pid = DATA1;
-
-	setbits_le32(usb_base + DWC_HCINT(control_msg.channel),
-		DWC_HCINT_XFERCOMP | DWC_HCINT_NAK | DWC_HCINT_ACK);
-	dwc_setup_transfer(control_msg);
-
-	/* status phase, shouldn't have any IN data, use a tmp variable
-	to read */
-	dwc_read_packet(control_msg, tmp);
-
-	setbits_le32(usb_base + DWC_HCINT(control_msg.channel),
-		DWC_HCINT_XFERCOMP);
-
-	/* nothing to send here, just remove the xfer complete status */
-	clrbits_le32(usb_base + DWC_HCINT(control_msg.channel),
-		DWC_HCINT_XFERCOMP);
-
-	return 0;
-}
-
-static int ctrlreq_in_data_phase(struct usb_device *dev, unsigned long pipe,
-				int len, void *buffer) {
-	usb_settoggle(dev, usb_pipeendpoint(pipe), 1, 0);
-	u32 rxlen = 0;
-	u32 nextlen = 0;
-	u8  maxpktsize = (1 << dev->maxpacketsize) * 8;
-	u32  *rxbuff = (u32 *)buffer;
-	u8  rxedlength;
-	struct packet control_msg;
-
-	while (rxlen < len) {
-		/* Determine the next read length */
-		nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen);
-
-		/* Set the ReqPkt bit */
-		control_msg.channel = 0;
-		control_msg.endpoint = 0;
-		control_msg.packet_count = 1;
-		control_msg.xfer_size = nextlen;
-		control_msg.ep_is_in = 1;
-		control_msg.devaddr = usb_pipedevice(pipe);
-		control_msg.type = EP_CTRL;
-		control_msg.mps = MAX_PACKET_SIZE;
-		control_msg.pid = DATA1;
-
-		__raw_writel(DWC_HCINT_ACK | DWC_HCINT_NAK,
-			usb_base + DWC_HCINT(control_msg.channel));
-		dwc_setup_transfer(control_msg);
-
-		rxedlength = dwc_read_packet(control_msg,
-			(u32 *)&rxbuff[rxlen]);
-
-		/* halt the channel... */
-		__raw_writel(
-			__raw_readl(usb_base + DWC_HCCHARN(control_msg.channel)
-			) | DWC_HCCHARN_CHDIS | DWC_HCCHARN_CHENA,
-			usb_base + DWC_HCCHARN(control_msg.channel));
-
-		u32 hcint = __raw_readl(
-			usb_base + DWC_HCINT(control_msg.channel));
-		while (!(hcint & (DWC_HCINT_CHHLTD))) {
-			hcint = __raw_readl(
-				usb_base + DWC_HCINT(control_msg.channel));
-			if (__raw_readl(usb_base + DWC_GINTSTS)
-				& DWC_GINTSTS_RXFLVL) {
-				__raw_readl(usb_base + DWC_GRXSTSP);
-			}
-		}
-		__raw_writel(DWC_HCINT_CHHLTD,
-			usb_base + DWC_HCINT(control_msg.channel));
-
-		/* clear xfer complete interrupt. */
-		__raw_writel(DWC_HCINT_XFERCOMP,
-			usb_base + DWC_HCINT(control_msg.channel));
-
-		/* short packet? */
-		if (rxedlength != nextlen) {
-			dev->act_len += rxedlength;
-			break;
-		}
-		rxlen += nextlen;
-		dev->act_len = rxlen;
-	}
-
-	return 0;
-}
-
-static int ctrlreq_out_status_phase(struct usb_device *dev, unsigned long pipe)
-{
-	struct packet control_msg;
-
-	usb_settoggle(dev, usb_pipeendpoint(pipe), 1, 0);
-
-	control_msg.channel = 0;
-	control_msg.endpoint = 0;
-	control_msg.packet_count = 1;
-	control_msg.xfer_size = 0;
-	control_msg.ep_is_in = 0;
-	control_msg.devaddr = usb_pipedevice(pipe);
-	control_msg.type = EP_CTRL;
-	control_msg.mps = MAX_PACKET_SIZE;
-	control_msg.pid = DATA1;
-
-	/* clear xfer complete interrupt. */
-	__raw_writel(DWC_HCINT_XFERCOMP,
-		usb_base + DWC_HCINT(control_msg.channel));
-
-	__raw_writel(DWC_HCINT_ACK | DWC_HCINT_NAK,
-		usb_base + DWC_HCINT(control_msg.channel));
-	dwc_setup_transfer(control_msg);
-
-	/* should wait for interrupt hcint here... */
-	if (dwc_wait_xfer_complete(control_msg.channel))
-		printf("DW_USB: Timed out waiting for xfer complete interrupt");
-
-	/* clear xfer complete interrupt. */
-	__raw_writel(DWC_HCINT_XFERCOMP,
-		usb_base + DWC_HCINT(control_msg.channel));
-
-	return 0;
-}
-
-/*
-* Interrupt not implemented, currently only supports mass storage
-*/
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-	int transfer_len, int interval) {
-	return -1;
-}
-
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-			int transfer_len, struct devrequest *setup) {
-	if (ctrlreq_setup_phase(dev, setup, pipe) < 0)
-		return -1;
-
-	if (usb_pipein(pipe)) {
-		if (ctrlreq_in_data_phase(dev, pipe, transfer_len, buffer) < 0)
-			return -1;
-		if (ctrlreq_out_status_phase(dev, pipe) < 0)
-			return -1;
-	} else {
-		if (ctrlreq_out_data_phase(dev, pipe, transfer_len, buffer) < 0)
-			return -1;
-		if (ctrlreq_in_status_phase(dev, pipe) < 0)
-			return -1;
-	}
-
-	dev->status = 0;
-	dev->act_len = transfer_len;
-
-	return transfer_len;
-}
-
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 69090c72ac..3ebcafbd90 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -370,11 +370,7 @@
 /*
  * USB
  */
-#define CONFIG_CMD_USB			1
 #define CONFIG_SYS_USB_ADDRESS SOCFPGA_USB1_ADDRESS
-#define CONFIG_USB_STORAGE		1
-#define CONFIG_USB_DWC_OTG_HCD		1
-#define CONFIG_DOS_PARTITION		1
 
 /*
  * L4 OSC1 Timer 0
diff --git a/include/usb.h b/include/usb.h
index 76f831afbb..1f2c85a975 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -149,8 +149,7 @@ struct usb_device {
 	defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
 	defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X) || \
 	defined(CONFIG_USB_MUSB_DSPS) || defined(CONFIG_USB_MUSB_AM35X) || \
-	defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_DWC_OTG_HCD) || \
-	defined(CONFIG_USB_DWC2_OTG)
+	defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_DWC2_OTG)
 
 int usb_lowlevel_init(int index, void **controller);
 int usb_lowlevel_stop(int index);