diff options
| author | Chin Liang See <clsee@altera.com> | 2014-08-08 15:01:45 +0800 |
|---|---|---|
| committer | Chin Liang See <clsee@altera.com> | 2014-08-08 15:01:45 +0800 |
| commit | cec58f7c8b8d54799348ffac0c1baf30b0c94bce (patch) | |
| tree | 016c85a7253989e1c741c96156e546a8dd275ba1 | |
| parent | 7b34d22af9506ab69dcf03bbfb96a78dcf2f5071 (diff) | |
| download | u-boot-socfpga-cec58f7c8b8d54799348ffac0c1baf30b0c94bce.tar.gz | |
mmc/dw_mmc: Fix clock divider calculation error for bypass mode
To fix the clock divider calculation error when the controller
clock same as the operating frequency. This is known as bypass
mode. In this mode, the divider should be 0.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Mischa Jonker <mjonker@synopsys.com>
| -rwxr-xr-x | drivers/mmc/dw_mmc.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index c8ace48f04..4a42a64707 100755 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -249,7 +249,10 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) return -EINVAL; } - div = DIV_ROUND_UP(sclk, 2 * freq); + if (sclk == freq) + div = 0; /* bypass mode */ + else + div = DIV_ROUND_UP(sclk, 2 * freq); dwmci_writel(host, DWMCI_CLKENA, 0); dwmci_writel(host, DWMCI_CLKSRC, 0); |