diff options
| author | Chin Liang See <clsee@altera.com> | 2013-02-07 11:07:04 +0800 |
|---|---|---|
| committer | Chin Liang See <clsee@altera.com> | 2013-02-07 11:07:04 +0800 |
| commit | e6a9d393aeff8c8bb775949d77ce51e043ddf3b9 (patch) | |
| tree | 9317162bdbaaa223ed904d3766e06d95df9a7a32 | |
| parent | d2860832db4617c520a4ef6fac7fe4ae1d645aec (diff) | |
| download | u-boot-socfpga-e6a9d393aeff8c8bb775949d77ce51e043ddf3b9.tar.gz | |
FogBugz #95141: Review - Update Preloader to execute on FPGA support
Update Preloader to execute on FPGA support.Repush as its already review but forget to push previously.
Signed-off-by: Chin Liang See <clsee@altera.com>
| -rw-r--r-- | arch/arm/cpu/armv7/socfpga/clock_manager.c | 10 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/socfpga/spl.c | 8 | ||||
| -rwxr-xr-x[-rw-r--r--] | arch/arm/cpu/armv7/socfpga/u-boot-spl-fpga.lds | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-socfpga/clock_manager.h | 2 |
4 files changed, 17 insertions, 5 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index 8e1f69b81e..c0c31e27f6 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -142,11 +142,13 @@ int cm_basic_init(const cm_config_t *cfg) readl(SOCFPGA_CLKMGR_ADDRESS + CLKMGR_PERPLLGRP_EN_ADDRESS), (SOCFPGA_CLKMGR_ADDRESS + CLKMGR_PERPLLGRP_EN_ADDRESS)); - /* DO NOT GATE OFF DEBUG CLOCKS */ + /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */ writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK | - CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK | - CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK | - CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK, + CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK | + CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK | + CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK | + CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK | + CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK, SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLLGRP_EN_ADDRESS); writel(0, SOCFPGA_CLKMGR_ADDRESS + CLKMGR_SDRPLLGRP_EN_ADDRESS); diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index c5a4373843..df146e3dd2 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -195,7 +195,9 @@ void spl_board_init(void) * to ensure no glitch happen during PLL re-configuration */ reset_assert_all_peripherals_except_l4wd0(); +#if (CONFIG_PRELOADER_EXE_ON_FPGA == 0) reset_assert_all_bridges(); +#endif DEBUG_MEMORY #ifdef CONFIG_SPL_SERIAL_SUPPORT @@ -308,8 +310,14 @@ void spl_board_init(void) debug("Deasserting resets\n"); #endif /* de-assert reset for peripherals and bridges based on handoff */ +#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET reset_deassert_peripherals_handoff(); +#else + reset_deassert_all_peripherals(); +#endif +#if (CONFIG_PRELOADER_EXE_ON_FPGA == 0) reset_deassert_bridges_handoff(); +#endif #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl-fpga.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl-fpga.lds index 3ebc6dc217..e558b2e52a 100644..100755 --- a/arch/arm/cpu/armv7/socfpga/u-boot-spl-fpga.lds +++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl-fpga.lds @@ -37,7 +37,7 @@ SECTIONS . = ALIGN(4); __data_start = .; - .data : AT (__data_start) { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + .data : AT (__data_start) { *(SORT_BY_ALIGNMENT(.data*)) } >.fpga . = ALIGN(4); __image_copy_end = .; diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h index 7f80571f0a..38d0665b6f 100644 --- a/arch/arm/include/asm/arch-socfpga/clock_manager.h +++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h @@ -105,10 +105,12 @@ extern int cm_basic_init(const cm_config_t *cfg); #define CLKMGR_ALTERAGRP_PERIMISC_ADDRESS 0xf0 #define CLKMGR_ALTERAGRP_SDRMMISC_ADDRESS 0xf4 +#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 #define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 #define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 #define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 #define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 +#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 #define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 2) & 0x00000004) #define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002) #define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001) |