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authorNitin Garg <nitin.garg@freescale.com>2014-04-02 08:55:01 -0500
committerVince Bridgers <vbridger@opensource.altera.com>2014-11-05 06:19:43 -0600
commit71282e2806669bdaa640688fa69f30705091e453 (patch)
treec9a10997524c5743127736ac527269eef2191fed
parent2fa71773fa9efd95aa47e2a6d87a5cc79a0f7cb3 (diff)
downloadu-boot-socfpga-71282e2806669bdaa640688fa69f30705091e453.tar.gz
ARM: Add workaround for Cortex-A9 errata 794072
A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
-rw-r--r--README1
-rw-r--r--arch/arm/cpu/armv7/start.S2
2 files changed, 2 insertions, 1 deletions
diff --git a/README b/README
index f78d14389b..421c1026ed 100644
--- a/README
+++ b/README
@@ -489,6 +489,7 @@ The following options need to be configured:
CONFIG_ARM_ERRATA_742230
CONFIG_ARM_ERRATA_743622
CONFIG_ARM_ERRATA_751472
+ CONFIG_ARM_ERRATA_794072
If set, the workarounds for these ARM errata are applied early
during U-Boot startup. Note that these options force the
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 306703a2f7..2d32235427 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -325,7 +325,7 @@ ENTRY(cpu_init_cp15)
mcr p15, 0, r0, c1, c0, 0 @ write system control register
#endif
-#ifdef CONFIG_ARM_ERRATA_742230
+#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 4 @ set bit #4
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register