spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max valuerel_socfpga_v2013.01.01_16.09.03_prrel_socfpga_v2013.01.01_16.09.02_prrel_socfpga_v2013.01.01_16.09.01_prACDS16.1_REL_GSRD_RC3ACDS16.1_REL_GSRD_RC2

Ensuring the baudrate divisor value doesn't exceed the max value
in the calculation.It will be capped at max value to ensure the
correct value being written into the register.

Example of the existing bug is when calculated div = 16. After and
with the mask, the value written to register is actually 0 (register
field for baudrate divisor). With this fix, the value written is now
15 which is max value for baudrate divisor.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
---
Changes for v2
- Remove the and operation with the mask
- Added more details on the issue

1 files changed, 5 insertions, 2 deletions

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index d69dc70f96..e8d71d9746 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -421,8 +421,11 @@ void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 	debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
 		ref_clk_hz, sclk_hz, div);
 
-	div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
-	reg |= div;
+	/* ensure the baud rate doesn't exceed the max value */
+	if (div > CQSPI_REG_CONFIG_BAUD_MASK)
+		div = CQSPI_REG_CONFIG_BAUD_MASK;
+
+	reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
 	CQSPI_WRITEL(reg, reg_base + CQSPI_REG_CONFIG);
 
 	cadence_qspi_apb_controller_enable(reg_base);