FogBugz #270904-85: allow early use of shared io pins

Fix double call to ddr_calibration_sequence()

Add support for external-fpga-config boolean in the chosen node
of the device tree.  When present, the code will wait forever for the
fpga to be programmed before exiting the function, s_init().  The intention
is to allow early usage of a uart that might be connected to shared ios.

With the sd-card code configuration, and no external-fpga-config property nor
cff_filename property in the chose node,  the code will ignore all fpga
programming and drop to the uboot prompt.  This is intended for use with a uart
connected to dedicated pins or semihosting.  This allows for manually executing
the "fpga loadfs" and "ddrcal" commands.

With the qspi code configuration, external-fpga-config in the chosen
node is honored, and s_init() will not be exited until the fpga
is programed by an external source.  If external-fpga-config is not present
in the chosen node, streaming the fpga image from qspi is attempted.

Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com>

10 files changed, 77 insertions, 31 deletions

diff --git a/arch/arm/cpu/armv7/socfpga_arria10/cff.c b/arch/arm/cpu/armv7/socfpga_arria10/cff.c
index 6b2c4a4b88..cf69215122 100755
--- a/arch/arm/cpu/armv7/socfpga_arria10/cff.c
+++ b/arch/arm/cpu/armv7/socfpga_arria10/cff.c
@@ -8,6 +8,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/misc.h>
 #include <fat.h>
 #include <fs.h>
 #include <mmc.h>
@@ -19,7 +21,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_MMC
-static const char *get_cff_filename(const void *fdt, int *len)
+const char *get_cff_filename(const void *fdt, int *len)
 {
 	const char *cff_filename = NULL;
 	const char *cell;
@@ -336,10 +338,14 @@ int socfpga_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
 
 		ret = cff_from_mmc_fat(fsinfo->dev_part, fsinfo->filename,
 				       slen);
-		if (ret > 0)
+		if (ret > 0) {
+			config_shared_fpga_pins(gd->fdt_blob);
+			reset_deassert_shared_connected_peripherals();
+			reset_deassert_fpga_connected_peripherals();
 			return FPGA_SUCCESS;
-		else
+		} else {
 			return FPGA_FAIL;
+		}
 	}
 #endif
 #ifdef CONFIG_CADENCE_QSPI
@@ -348,6 +354,9 @@ int socfpga_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
 		u32 rbfaddr = simple_strtoul(fsinfo->dev_part, NULL, 16);
 		ret = cff_from_qspi(rbfaddr);
 		if (ret > 0)
+			config_shared_fpga_pins(gd->fdt_blob);
+			reset_deassert_shared_connected_peripherals();
+			reset_deassert_fpga_connected_peripherals();
 			return FPGA_SUCCESS;
 		else
 			return FPGA_FAIL;
diff --git a/arch/arm/cpu/armv7/socfpga_arria10/misc.c b/arch/arm/cpu/armv7/socfpga_arria10/misc.c
index 9aebdf7d22..65e4d80367 100755
--- a/arch/arm/cpu/armv7/socfpga_arria10/misc.c
+++ b/arch/arm/cpu/armv7/socfpga_arria10/misc.c
@@ -14,6 +14,7 @@
 #include <asm/arch/dwmmc.h>
 #include <altera.h>
 #include <dwmmc.h>
+#include <fdtdec.h>
 #include <fpga.h>
 #include <mmc.h>
 #include <netdev.h>
@@ -166,3 +167,16 @@ void skip_relocation(void)
 	board_init_r(id, (CONFIG_SYS_INIT_SP_ADDR - CONFIG_OCRAM_STACK_SIZE));
 }
 
+int is_external_fpga_config(const void *blob)
+{
+	int node, len;
+	int rval = 0;
+
+	node = fdt_subnode_offset(blob, 0, "chosen");
+	if (node >= 0) {
+		if (fdt_getprop(blob, node, "external-fpga-config", &len))
+			rval = 1;
+	}
+
+	return rval;
+}
diff --git a/arch/arm/cpu/armv7/socfpga_arria10/s_init.c b/arch/arm/cpu/armv7/socfpga_arria10/s_init.c
index 5ed53fd925..7a0638ee01 100755
--- a/arch/arm/cpu/armv7/socfpga_arria10/s_init.c
+++ b/arch/arm/cpu/armv7/socfpga_arria10/s_init.c
@@ -7,10 +7,12 @@
 #include <common.h>
 #include <asm/io.h>
 #include <watchdog.h>
+#include <asm/arch/fpga_manager.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/system_manager.h>
 #include <asm/arch/clock_manager.h>
 #include <asm/arch/ecc_ram.h>
+#include <asm/arch/misc.h>
 #include <asm/arch/sdram.h>
 #include <asm/sections.h>
 #include <fdtdec.h>
@@ -184,7 +186,12 @@ void s_init(void)
 	/* configure the Reset Manager */
 	reset_deassert_dedicated_peripherals();
 
-	/* If fpga is already loaded, calibrate ddr and enable
-	   fpga bridges */
-	ddr_calibration_sequence();
+	if (is_external_fpga_config(gd->fdt_blob)) {
+		while (!is_fpgamgr_user_mode())
+			;
+
+		config_shared_fpga_pins(gd->fdt_blob);
+		reset_deassert_shared_connected_peripherals();
+		reset_deassert_fpga_connected_peripherals();
+	}
 }
diff --git a/arch/arm/cpu/armv7/socfpga_arria10/sdram.c b/arch/arm/cpu/armv7/socfpga_arria10/sdram.c
index 410369486c..2a20012a8f 100644
--- a/arch/arm/cpu/armv7/socfpga_arria10/sdram.c
+++ b/arch/arm/cpu/armv7/socfpga_arria10/sdram.c
@@ -18,7 +18,6 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/system_manager.h>
 
-int config_shared_fpga_pins(const void *blob);
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -1096,18 +1095,6 @@ int ddr_calibration_sequence(void)
 
 	WATCHDOG_RESET();
 
-	reset_assert_uart();
-
-	config_shared_fpga_pins(gd->fdt_blob);
-
-	reset_deassert_uart();
-	reset_deassert_shared_connected_peripherals();
-	reset_deassert_fpga_connected_peripherals();
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-		     ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM1,
-					   CONFIG_SYS_NS16550_CLK,
-					   CONFIG_BAUDRATE));
 
 	of_get_sdr_cfg(gd->fdt_blob, &cfg);
 
@@ -1145,6 +1132,7 @@ int dram_init(void)
 {
 	bd_t *bd;
 	unsigned long addr;
+	int rval = 0;
 
 	WATCHDOG_RESET();
 
@@ -1179,18 +1167,38 @@ int dram_init(void)
 		- CONFIG_OCRAM_STACK_SIZE - CONFIG_OCRAM_MALLOC_SIZE;
 	mem_malloc_init(malloc_start, CONFIG_OCRAM_MALLOC_SIZE);
 
-#ifdef CONFIG_MMC
-	mmc_initialize(gd->bd);
+	if (is_external_fpga_config(gd->fdt_blob)) {
+		ddr_calibration_sequence();
+	} else {
+#if defined(CONFIG_MMC)
+		int len = 0;
+		const char *cff = get_cff_filename(gd->fdt_blob, &len);
+		if (cff && (len > 0)) {
+			mmc_initialize(gd->bd);
 
-	cff_from_mmc_fat_dt();
-#endif
-#ifdef CONFIG_CADENCE_QSPI
-	/* do I need this if, or just superflous? */
-	if (!is_fpgamgr_user_mode())
-		cff_from_qspi_env();
+			rval = cff_from_mmc_fat("0:1", cff, len);
+		}
+#elif defined(CONFIG_CADENCE_QSPI)
+		rval = cff_from_qspi_env();
+#else
+#error "unsupported config"
 #endif
-
-	ddr_calibration_sequence();
+		if (rval > 0) {
+			reset_assert_uart();
+			config_shared_fpga_pins(gd->fdt_blob);
+			reset_deassert_uart();
+
+			reset_deassert_shared_connected_peripherals();
+			reset_deassert_fpga_connected_peripherals();
+			NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+				     ns16550_calc_divisor(
+					     (NS16550_t)CONFIG_SYS_NS16550_COM1,
+					     CONFIG_SYS_NS16550_CLK,
+					     CONFIG_BAUDRATE));
+
+			ddr_calibration_sequence();
+		}
+	}
 
 	/* Skip relocation as U-Boot cannot run on SDRAM for secure boot */
 	skip_relocation();
@@ -1222,4 +1230,3 @@ void dram_bank_mmu_setup(int bank)
 	set_section_dcache(i, DCACHE_WRITEBACK);
 #endif
 }
-
diff --git a/arch/arm/dts/socfpga_arria10.dts b/arch/arm/dts/socfpga_arria10.dts
index 47dd5d56c6..1563639442 100644
--- a/arch/arm/dts/socfpga_arria10.dts
+++ b/arch/arm/dts/socfpga_arria10.dts
@@ -13,6 +13,7 @@
 	chosen {
 		cff-file = "ghrd_10as066n2.periph.rbf",
 			"ghrd_10as066n2.core.rbf";
+		/* external-fpga-config; */
 	};
 
 	clocks {
diff --git a/arch/arm/dts/socfpga_arria10_dedicated_uart.dts b/arch/arm/dts/socfpga_arria10_dedicated_uart.dts
index 9ce854068e..2082b1c5ba 100644
--- a/arch/arm/dts/socfpga_arria10_dedicated_uart.dts
+++ b/arch/arm/dts/socfpga_arria10_dedicated_uart.dts
@@ -13,6 +13,7 @@
 	chosen {
 		cff-file = "ghrd_10as066n2.periph.rbf",
 			"ghrd_10as066n2.core.rbf";
+		/* external-fpga-config; */
 	};
 
 	clocks {
diff --git a/arch/arm/dts/socfpga_arria10_qspi.dts b/arch/arm/dts/socfpga_arria10_qspi.dts
index 54ec2cbd2d..2e698615ab 100644
--- a/arch/arm/dts/socfpga_arria10_qspi.dts
+++ b/arch/arm/dts/socfpga_arria10_qspi.dts
@@ -11,7 +11,7 @@
 
 
 	chosen {
-		cff-file = "soc_system.rbf";
+		/* external-fpga-config; */
 	};
 
 	clocks {
diff --git a/arch/arm/dts/socfpga_arria10_qspi_dedicated_uart.dts b/arch/arm/dts/socfpga_arria10_qspi_dedicated_uart.dts
index 2c7df0f281..1abf039b6a 100644
--- a/arch/arm/dts/socfpga_arria10_qspi_dedicated_uart.dts
+++ b/arch/arm/dts/socfpga_arria10_qspi_dedicated_uart.dts
@@ -11,6 +11,7 @@
 
 
 	chosen {
+		/* external-fpga-config; */
 	};
 
 	clocks {
diff --git a/arch/arm/include/asm/arch-socfpga_arria10/cff.h b/arch/arm/include/asm/arch-socfpga_arria10/cff.h
index 5e6bbe608d..577cf649bc 100755
--- a/arch/arm/include/asm/arch-socfpga_arria10/cff.h
+++ b/arch/arm/include/asm/arch-socfpga_arria10/cff.h
@@ -10,6 +10,9 @@
 #ifndef __ASSEMBLY__
 int cff_from_mmc_fat_dt(void);
 int cff_from_qspi_env(void);
+int cff_from_qspi(unsigned long flash_offset);
+const char *get_cff_filename(const void *fdt, int *len);
+int cff_from_mmc_fat(char *dev_part, const char *filename, int len);
 #endif /* __ASSEMBLY__ */
 
 #endif /* _SOCFPGA_CFF_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga_arria10/misc.h b/arch/arm/include/asm/arch-socfpga_arria10/misc.h
index a1145fa197..8f3d49f6da 100755
--- a/arch/arm/include/asm/arch-socfpga_arria10/misc.h
+++ b/arch/arm/include/asm/arch-socfpga_arria10/misc.h
@@ -9,6 +9,9 @@
 
 #ifndef __ASSEMBLY__
 void skip_relocation(void);
+int is_external_fpga_config(const void *blob);
+int config_shared_fpga_pins(const void *blob);
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _SOCFPGA_MISC_H_ */