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| author | Chin Liang See <chin.liang.see@intel.com> | 2018-03-27 23:24:29 +0800 |
|---|---|---|
| committer | Chin Liang See <chin.liang.see@intel.com> | 2018-03-27 23:24:29 +0800 |
| commit | 03db6f4894450a0a8b80478a8567a7353cb2ab99 (patch) | |
| tree | e9b571269dee27effbf159ddbb1191007ec54b5a | |
| parent | c85cd1fc1331210f1c22adb29d932d4052f79c78 (diff) | |
| download | u-boot-socfpga-03db6f4894450a0a8b80478a8567a7353cb2ab99.tar.gz | |
FogBugz #544650: Ensure watchdog paused when debuggingrel_socfpga_v2017.09_18.04.01_prACDS18.0_REL_S10_GSRD_PR
Fix debugging timeout issue where watchdog is not paused when
debugging with debugger. This patch will ensure all watchdogs
are paused when one of the CPU is in debugging state.
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
Changes for v3 & v2
- Updated the commit message
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/system_manager_s10.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/spl_s10.c | 3 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h index 94ea995308..81b5665fc9 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h @@ -171,4 +171,6 @@ struct socfpga_system_manager { #define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF +#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F + #endif /* _SYSTEM_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index db4962e6b0..3346444026 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -54,6 +54,9 @@ void board_init_f(ulong dummy) const struct cm_config *cm_default_cfg = cm_get_default_config(); #ifdef CONFIG_HW_WATCHDOG + /* Ensure watchdog is paused when debugging is happening */ + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg); + /* Enable watchdog before initializing the HW */ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); |