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| author | Chin Liang See <chin.liang.see@intel.com> | 2017-09-15 21:57:01 +0800 |
|---|---|---|
| committer | Chin Liang See <chin.liang.see@intel.com> | 2017-09-18 16:10:31 +0800 |
| commit | 0b8d870f02390132e0c34a14658011f8bf2c0802 (patch) | |
| tree | 6185d2b5710fa24cf630875824697f7efa7f6b9b | |
| parent | f8eab1d1b5876a97cca02c34a247a499a317b5f3 (diff) | |
| download | u-boot-socfpga-0b8d870f02390132e0c34a14658011f8bf2c0802.tar.gz | |
arm: socfpga: stratix10: Add timer support for Stratix10 SoC
Add timer support for Stratix SoC
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
| -rw-r--r-- | arch/arm/mach-socfpga/timer.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c index 253cde39d1..4ae8ac1065 100644 --- a/arch/arm/mach-socfpga/timer.c +++ b/arch/arm/mach-socfpga/timer.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * Copyright (C) 2012-2016 Altera Corporation <www.altera.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,15 +11,29 @@ #define TIMER_LOAD_VAL 0xFFFFFFFF +#ifdef CONFIG_TARGET_SOCFPGA_GEN5 static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; +#endif /* * Timer initialization */ int timer_init(void) { +#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) + int enable = 0x3; /* timer enable + output signal masked */ + int loadval = ~0; + + /* enable system counter */ + writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS); + /* enable processor pysical counter */ + asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable)); + asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval)); + +#else writel(TIMER_LOAD_VAL, &timer_base->load_val); writel(TIMER_LOAD_VAL, &timer_base->curr_val); writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl); +#endif return 0; } |