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| author | Chin Liang See <chin.liang.see@intel.com> | 2018-01-05 23:50:01 +0800 |
|---|---|---|
| committer | Chin Liang See <chin.liang.see@intel.com> | 2018-01-19 14:23:19 +0800 |
| commit | a178b66739270fdc38ca5acc49352e763dbf7c6c (patch) | |
| tree | a961c4a48e0086a984a6ba32f73894d9189f28b4 | |
| parent | ab221d6b0903645892fb19e3889cd990024ffabe (diff) | |
| download | u-boot-socfpga-a178b66739270fdc38ca5acc49352e763dbf7c6c.tar.gz | |
FogBugz #524232: spi: cadence_qspi: Support various address cells size
Enhance initialization code so it can extract the correct addresses
from reg field even with various address-cells value.
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
| -rw-r--r-- | drivers/spi/cadence_qspi.c | 15 |
1 files changed, 3 insertions, 12 deletions
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 9a6e41f330..39cb9a86fd 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -208,7 +208,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen, } else { data_bytes = bitlen / 8; } - debug("%s: len=%d [bytes]\n", __func__, data_bytes); + debug("%s: len=%d [bytes]\n", __func__, (int)data_bytes); /* Set Chip select */ cadence_qspi_apb_chipselect(base, spi_chip_select(dev), @@ -284,18 +284,9 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) const void *blob = gd->fdt_blob; int node = dev_of_offset(bus); int subnode; - u32 data[4]; - int ret; - /* 2 base addresses are needed, lets get them from the DT */ - ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data)); - if (ret) { - printf("Error: Can't get base addresses (ret=%d)!\n", ret); - return -ENODEV; - } - - plat->regbase = (void *)data[0]; - plat->ahbbase = (void *)data[2]; + plat->regbase = (void *)devfdt_get_addr_index(bus, 0); + plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1); plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); /* All other paramters are embedded in the child node */ |