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| author | Thor Thayer <thor.thayer@linux.intel.com> | 2017-12-19 10:14:59 -0600 |
|---|---|---|
| committer | Thor Thayer <thor.thayer@linux.intel.com> | 2018-01-03 12:57:54 -0600 |
| commit | ab221d6b0903645892fb19e3889cd990024ffabe (patch) | |
| tree | f3ba3a1a440c65e976e84710be38bd28e6309d8f | |
| parent | 131cc3b1e991613484b05c8db59d365c37ba415d (diff) | |
| download | u-boot-socfpga-ab221d6b0903645892fb19e3889cd990024ffabe.tar.gz | |
FogBugz #514871: arm: socfpga: stratix10: Enable SPI1 support
Enable SPIM1 support for SOCFPGA Stratix10 SoC Daughtercard or
SPI Loopback testing.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
| -rwxr-xr-x | arch/arm/mach-socfpga/spl_s10.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index 7ab3bb9fe0..f94226bd69 100755 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -139,6 +139,8 @@ void board_init_f(ulong dummy) socfpga_per_reset(SOCFPGA_RESET(USB1), 0); socfpga_per_reset(SOCFPGA_RESET(USB0_OCP), 0); socfpga_per_reset(SOCFPGA_RESET(USB1_OCP), 0); + /* enable SPIM1 */ + socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); /* disable lwsocf2fpga and soc2fpga bridge security */ writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA); |