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| author | Thor Thayer <thor.thayer@linux.intel.com> | 2019-11-13 15:31:44 -0600 |
|---|---|---|
| committer | Thor Thayer <thor.thayer@linux.intel.com> | 2019-11-13 15:33:48 -0600 |
| commit | a76dcc03f6fd307fca42d58e5f149e5c0078f929 (patch) | |
| tree | 2387a4230d78d3660622f22fb8f8168bbce8c258 | |
| parent | 8c742720dd7aeb99dce2f0715621a1e7cf025195 (diff) | |
| download | u-boot-socfpga-a76dcc03f6fd307fca42d58e5f149e5c0078f929.tar.gz | |
HSD #1707105006: Stratix10: Fix SMMU accessrel_socfpga_v2017.09_19.12.01_rc1rel_socfpga_v2017.09_19.12.01_prrel_socfpga_v2017.09_19.11.03_pr
Enable TCU access through the Stratix10 CCU so that the
SMMU can access the SDRAM. This corrects the removal of
the TCU in
Commit ab35b5178a83 ("HSD #1409755457-11: arm: socfpga: Move
Stratix 10 SDRAM driver to DM")
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/firewall_s10.h | 7 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/sdram_s10.h | 22 | ||||
| -rwxr-xr-x | drivers/ddr/altera/sdram_s10.c | 14 |
3 files changed, 21 insertions, 22 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h b/arch/arm/mach-socfpga/include/mach/firewall_s10.h index 7d796754bc..9e5941708d 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall_s10.h +++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h @@ -101,6 +101,13 @@ struct socfpga_firwall_l4_sys { #define CCU_IOM_MPRT_ADMASK_MEM_RAM0 0x18628 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE0 0x2c520 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1A 0x2c540 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1B 0x2c560 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1C 0x2c580 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1D 0x2c5a0 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1E 0x2c5c0 + #define CCU_REG_ADDR(reg) \ (SOCFPGA_CCU_ADDRESS + (reg)) diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h index 1b23716e79..b8aa6099c2 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h @@ -335,28 +335,6 @@ union caltiming9_reg { #define DDR_HMC_SEQ2CORE_INT_RESP_MASK 0x8 #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f -#define CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR 0xf7004400 -#define CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR 0xf70045c0 -#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR 0xf70045e0 -#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR 0xf7004600 -#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR 0xf7004620 -#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR 0xf7004640 -#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR 0xf7004660 - -#define CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR 0xf7018560 -#define CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR 0xf7018580 -#define CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR 0xf70185a0 -#define CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR 0xf70185c0 -#define CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR 0xf70185e0 -#define CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR 0xf7018600 - -#define CCU_TCU_MPRT_ADBASE_MEMSPACE0_ADDR 0xf702c520 -#define CCU_TCU_MPRT_ADBASE_MEMSPACE1A_ADDR 0xf702c540 -#define CCU_TCU_MPRT_ADBASE_MEMSPACE1B_ADDR 0xf702c560 -#define CCU_TCU_MPRT_ADBASE_MEMSPACE1C_ADDR 0xf702c580 -#define CCU_TCU_MPRT_ADBASE_MEMSPACE1D_ADDR 0xf702c5a0 -#define CCU_TCU_MPRT_ADBASE_MEMSPACE1E_ADDR 0xf702c5c0 - #define CCU_ADBASE_DI_MASK 0x00000010 #define FW_HMC_ADAPTOR_ADDR 0xf8020004 diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 50b5a79e4a..276ca212cc 100755 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -322,6 +322,20 @@ static int sdram_mmr_init_full(struct udevice *dev) clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E), CCU_ADBASE_DI_MASK); + /* Enable access to DDR from TCU */ + clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E), + CCU_ADBASE_DI_MASK); + /* this enables nonsecure access to DDR */ /* mpuregion0addr_limit */ FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT); |