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| author | Chee Hong Ang <chee.hong.ang@intel.com> | 2019-12-23 20:24:41 +0800 |
|---|---|---|
| committer | Chee Hong Ang <chee.hong.ang@intel.com> | 2019-12-24 12:47:29 +0800 |
| commit | 83e929c739beecff17529a0cf0fdd5c74fbe3c72 (patch) | |
| tree | 661995cb158658e9b21a0181f818f69f6d30760f | |
| parent | ba2ae15f719eadd2bcdcbfca69dfcbf1bb5563ed (diff) | |
| download | u-boot-socfpga-83e929c739beecff17529a0cf0fdd5c74fbe3c72.tar.gz | |
HSD #1507121804: configs: socfpga: stratix10: UART clock no longer hardcodedrel_socfpga_v2019.04_20.01.01_rc1rel_socfpga_v2019.04_20.01.01_pr
Instead of hardcoded the UART clock's frquency, now it is derived from the
clock manager 'get clock' function.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
| -rw-r--r-- | include/configs/socfpga_stratix10_socdk.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h index d1c0f40e02..55144e8611 100644 --- a/include/configs/socfpga_stratix10_socdk.h +++ b/include/configs/socfpga_stratix10_socdk.h @@ -166,7 +166,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * Serial / UART configurations */ -#define CONFIG_SYS_NS16550_CLK 100000000 +#ifndef __ASSEMBLY__ +unsigned int cm_get_l4_sp_clk_hz(void); +#endif +#define CONFIG_SYS_NS16550_CLK cm_get_l4_sp_clk_hz() #define CONFIG_SYS_NS16550_MEM32 /* |