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author | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-11-06 16:48:47 +0800 |
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committer | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-11-12 13:31:31 +0800 |
commit | 4af6bfdcbd3f3394941033a93edc23e3a67008c3 (patch) | |
tree | 4e0b027aff47ba99d3e31802f232c344fd92909f | |
parent | 1b4745964d3f3fa79ca44b68bc893011aedfb6b1 (diff) | |
download | u-boot-socfpga-4af6bfdcbd3f3394941033a93edc23e3a67008c3.tar.gz |
HSD #1507526426-5: clk: agilex: Add clock enable support
Some drivers probing failed if clock enable function is not supported in
clock driver. So, add clock enable function to clock driver to solve it.
Return 0 (success) for *.enable function because all clocks are enabled
by default in clock driver probe.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
-rw-r--r-- | drivers/clk/altera/clk-agilex.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index 4cbc62782c..697ef69854 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -540,6 +540,11 @@ static ulong socfpga_clk_get_rate(struct clk *clk) } } +static int socfpga_clk_enable(struct clk *clk) +{ + return 0; +} + static int socfpga_clk_probe(struct udevice *dev) { const struct cm_config *cm_default_cfg = cm_get_default_config(); @@ -563,6 +568,7 @@ static int socfpga_clk_ofdata_to_platdata(struct udevice *dev) } static struct clk_ops socfpga_clk_ops = { + .enable = socfpga_clk_enable, .get_rate = socfpga_clk_get_rate, }; |