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| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2021-05-10 22:25:33 -0700 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2021-05-23 20:08:27 -0700 |
| commit | 21d8c90bef6bf954ad386301dfea7b0811911c9a (patch) | |
| tree | da410748d37aea518609bfa6bcf31faaf40ba02b | |
| parent | 8c83efcd95a7b19cd203eb59c36d3c06576eacd6 (diff) | |
| download | u-boot-socfpga-21d8c90bef6bf954ad386301dfea7b0811911c9a.tar.gz | |
arm: dts: n5x: User interface for DDR self-refresh configuration
These are interface for users to customize some settings in DDR
self-refresh configuration according to their design requirement.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| -rw-r--r-- | arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi index 57509f083e..59f58d6771 100644 --- a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi @@ -13,6 +13,12 @@ i2c0 = &i2c1; }; + fs_loader0: fs-loader { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + sfconfig = <0 0 100000000 3>; + }; + memory { /* * Memory type: DDR4 @@ -37,6 +43,13 @@ }; }; +&sdr { + intel,ddrcal-qspi-offset = "0x7000000"; + intel,ddrcal-ddr-offset = "0x100000"; + firmware-loader = <&fs_loader0>; + u-boot,dm-pre-reloc; +}; + &flash0 { compatible = "jedec,spi-nor"; spi-tx-bus-width = <4>; |