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| author | Yau Wai Gan <yau.wai.gan@intel.com> | 2021-04-14 10:17:11 +0800 |
|---|---|---|
| committer | Yau Wai Gan <yau.wai.gan@intel.com> | 2021-04-14 15:59:35 +0800 |
| commit | a2fdf8224f33e96427211cdacd90da3c3c6eea81 (patch) | |
| tree | db6a12b5261de75f7cdb641ce7ba796aa1bac848 | |
| parent | ce717aa87c91a2edd9cd9572ed9c98cebe4296db (diff) | |
| download | u-boot-socfpga-a2fdf8224f33e96427211cdacd90da3c3c6eea81.tar.gz | |
drivers: fpga: intel_sdm_mb: Flush cache before FPGA configuration
FPGA configuration encounter failure when the cache is not flushed.
Add cache flushing to the memory region that holds the FPGA
configuration bitstream.
Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
| -rw-r--r-- | drivers/fpga/intel_sdm_mb.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c index 1c23cae563..0ebd7ef10f 100644 --- a/drivers/fpga/intel_sdm_mb.c +++ b/drivers/fpga/intel_sdm_mb.c @@ -10,6 +10,8 @@ #include <asm/arch/mailbox_s10.h> #include <asm/arch/smc_api.h> #include <asm/arch/smmu_s10.h> +#include <asm/cache.h> +#include <cpu_func.h> #include <linux/delay.h> #include <linux/intel-smc.h> @@ -123,6 +125,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) debug("Invoking FPGA_CONFIG_START...\n"); + flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size)); + ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0); if (ret) { @@ -396,6 +400,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) u32 resp_len = 2; u32 resp_buf[2]; + flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size)); + /* * Don't start the FPGA reconfiguration if bitstream location exceed the * PSI BE 512MB address window and SMMU is not setup for PSI BE address |