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| author | Lokanathan, Raaj <raaj.lokanathan@intel.com> | 2021-12-08 18:03:25 +0800 |
|---|---|---|
| committer | Lokanathan, Raaj <raaj.lokanathan@intel.com> | 2021-12-08 18:03:25 +0800 |
| commit | 3e469145a07b0cb74567aa67042f636b4e73c485 (patch) | |
| tree | 9f84a02391c68be89e81c89e40dc828b8d748c60 | |
| parent | 772e4b282429b2d9f7fc6c2d22c7611b799d2db3 (diff) | |
| download | u-boot-socfpga-3e469145a07b0cb74567aa67042f636b4e73c485.tar.gz | |
HSD #16015333053: configs: socfpga: Disable QSPI config in SPL of CV defconfigrel_socfpga_v2021.10_RC_22.02.02_prrel_socfpga_v2021.10_RC_22.02.01_prrel_socfpga_v2021.10_RC_22.01.03_prrel_socfpga_v2021.10_RC_22.01.02_prrel_socfpga_v2021.10_RC_22.01.01_prrel_socfpga_v2021.10_RC_21.12.03_prsocfpga_v2021.10_RC
The mainline have added new Cadence QSPI driver code which causes the code size
to overblown in the Cyclone V. This causes the Cyclone V SPL cannot fit into the
64kb on chip RAM. By disabling the QSPI defconfig in the SPL of Cyclone V
defconfig, the SPL code size able to reduce.
Signed-off-by: Raaj Lokanathan <raaj.lokanathan@intel.com>
| -rw-r--r-- | configs/socfpga_cyclone5_defconfig | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 5c32741ad1..2d53b235e8 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -6,6 +6,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y +# CONFIG_SPL_SPI_SUPPORT is not set CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_BOOTCOMMAND="run fatscript;bridge enable; run distro_bootcmd" @@ -15,8 +16,6 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y |