diff options
| author | Lokanathan, Raaj <raaj.lokanathan@intel.com> | 2022-03-30 15:35:12 +0800 |
|---|---|---|
| committer | Lokanathan, Raaj <raaj.lokanathan@intel.com> | 2022-06-14 19:01:56 +0800 |
| commit | 0f852c122b5bc91b50072c85171f1a6e3d31c004 (patch) | |
| tree | 473e5a6490e08365f78c7f5dbdeab04270829b33 | |
| parent | 8ce5bdb8e0a373585c8da8d3416105c994de66df (diff) | |
| download | u-boot-socfpga-0f852c122b5bc91b50072c85171f1a6e3d31c004.tar.gz | |
HSD #18019787883: arm: socfpga: Expand the help text for the bridge command.
The existing bridge command is incomplete and it has spelling error. This newly
added help text indicates the bit positions and the values of the mask.
ie: bit 0 = h2f/s2f, bit 1 = lwhps2fpga, and bit 2 = f2h/f2s
These bridges available only in Stratix 10:
bit3: f2sdram0
bit4: f2sdram1
bit5: f2sdram2
Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
| -rw-r--r-- | arch/arm/mach-socfpga/misc.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index d0f23d7000..af36ad48f6 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -209,8 +209,9 @@ static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc, U_BOOT_CMD(bridge, 3, 1, do_bridge, "SoCFPGA HPS FPGA bridge control", - "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges \n" + "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges\n" + "Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10\n" "" ); |