diff options
| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2022-03-01 15:18:36 +0800 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2022-04-07 10:50:22 +0800 |
| commit | 400442762324d2e0f10f2bc96510768256ee5f5d (patch) | |
| tree | 02d7fa90f994f882ef2fe6c5bd5942b4e7ff5d34 | |
| parent | 5750205db17e3f5dce84159a8abcbd591c26194e (diff) | |
| download | u-boot-socfpga-400442762324d2e0f10f2bc96510768256ee5f5d.tar.gz | |
HSD #18020445323-10: arm: dts: soc64: Move OCRAM CCU config to DTS
Centralizing both agilex and n5x CCU config of OCRAM related
accesses in DTS.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| -rw-r--r-- | arch/arm/dts/socfpga_agilex-u-boot.dtsi | 11 | ||||
| -rw-r--r-- | arch/arm/dts/socfpga_n5x-u-boot.dtsi | 11 | ||||
| -rw-r--r-- | drivers/cache/cache-ncore.c | 18 |
3 files changed, 22 insertions, 18 deletions
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi index 3efb108660..ca71afa2c1 100644 --- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi @@ -86,6 +86,17 @@ }; &socfpga_secreg { + CCU_coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 { + reg = <0xf7100200 0x00000014>; + intel,offset-settings = + /* Disable ocram security at CCU for non secure access */ + <0x0000004 0x8000ffff>, + <0x0000008 0x8000ffff>, + <0x000000c 0x8000ffff>, + <0x0000010 0x8000ffff>; + u-boot,dm-pre-reloc; + }; + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { reg = <0xf8020000 0x0000001c>; intel,offset-settings = diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi index 104dbbeea7..65d874a5a1 100644 --- a/arch/arm/dts/socfpga_n5x-u-boot.dtsi +++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi @@ -135,6 +135,17 @@ }; &socfpga_secreg { + coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 { + reg = <0xf7100200 0x00000014>; + intel,offset-settings = + /* Disable ocram security at CCU for non secure access */ + <0x0000004 0x8000ffff>, + <0x0000008 0x8000ffff>, + <0x000000c 0x8000ffff>, + <0x0000010 0x8000ffff>; + u-boot,dm-pre-reloc; + }; + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { reg = <0xf8020000 0x0000001c>; intel,offset-settings = diff --git a/drivers/cache/cache-ncore.c b/drivers/cache/cache-ncore.c index f7b4906bbd..8926f15c43 100644 --- a/drivers/cache/cache-ncore.c +++ b/drivers/cache/cache-ncore.c @@ -43,13 +43,6 @@ #define CCU_DIR_REG_ADDR(base, reg, dir) \ ((base) + (reg) + ((dir) * DIR_REG_SZ)) -/* OCRAM firewall register */ -#define OCRAM_FW_01 0x100204 -#define OCRAM_SECURE_REGIONS 4 - -#define OCRAM_PRIVILEGED_MASK BIT(29) -#define OCRAM_SECURE_MASK BIT(30) - static void ncore_ccu_init_dirs(void __iomem *base) { ulong i, f; @@ -124,16 +117,6 @@ static void ncore_ccu_init_coh_agent(void __iomem *base) } } -static void ocram_bypass_firewall(void __iomem *base) -{ - int i; - - for (i = 0; i < OCRAM_SECURE_REGIONS; i++) { - clrbits_le32(base + OCRAM_FW_01 + (i * sizeof(u32)), - OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK); - } -} - static int ncore_ccu_probe(struct udevice *dev) { void __iomem *base; @@ -147,7 +130,6 @@ static int ncore_ccu_probe(struct udevice *dev) ncore_ccu_init_dirs(base); ncore_ccu_init_coh_agent(base); - ocram_bypass_firewall(base); return 0; } |