diff options
| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2022-02-24 11:40:56 +0800 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2022-04-07 10:50:21 +0800 |
| commit | 61043fffc5d481845391d18408a51171f51ce48a (patch) | |
| tree | 1a84d103f2821f3a29691df26915c55fbf8eff0e | |
| parent | b80f0f6b0b5906ad62da93747659db45ee212078 (diff) | |
| download | u-boot-socfpga-61043fffc5d481845391d18408a51171f51ce48a.tar.gz | |
HSD #18020445323-4: arm: dts: s10: Add fpga2sdram FW settings
Adding all fpga2sdram firewall settings with default reset value
in DTS for the sake of easy reference by user.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| -rw-r--r-- | arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi index a0f763c0f6..d1565e073f 100644 --- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi @@ -48,4 +48,88 @@ <0x00010640 0x00000000>; u-boot,dm-pre-reloc; }; + + /* + * Both firewall and QOS regs accessed by CPU in MPFE has + * dependency on CCU configuration above. + * + * Below are all fpga2sdram firewall settings with default + * reset value for the sake of easy reference by users. + * Users may choose to remove any of these register configurations + * that they do not require in their specific implementation. + */ + soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr@f8020200 { + reg = <0xf8020200 0x00000050>; + intel,offset-settings = + <0x0000000 0x00000000>, + <0x0000004 0x00000000>, + <0x0000008 0x00000000>, + <0x0000010 0x00000000>, + <0x0000014 0x00000000>, + <0x0000018 0x0000ffff>, + <0x000001c 0x00000000>, + <0x0000020 0x00000000>, + <0x0000024 0x00000000>, + <0x0000028 0x0000ffff>, + <0x000002c 0x00000000>, + <0x0000030 0x00000000>, + <0x0000034 0x00000000>, + <0x0000038 0x0000ffff>, + <0x000003c 0x00000000>, + <0x0000040 0x00000000>, + <0x0000044 0x00000000>, + <0x0000048 0x0000ffff>, + <0x000004c 0x00000000>; + u-boot,dm-pre-reloc; + }; + + soc_noc_fw_ddr_fpga2sdram_inst_1_ddr_scr@f8020300 { + reg = <0xf8020300 0x00000050>; + intel,offset-settings = + <0x0000000 0x00000000>, + <0x0000004 0x00000000>, + <0x0000008 0x00000000>, + <0x0000010 0x00000000>, + <0x0000014 0x00000000>, + <0x0000018 0x0000ffff>, + <0x000001c 0x00000000>, + <0x0000020 0x00000000>, + <0x0000024 0x00000000>, + <0x0000028 0x0000ffff>, + <0x000002c 0x00000000>, + <0x0000030 0x00000000>, + <0x0000034 0x00000000>, + <0x0000038 0x0000ffff>, + <0x000003c 0x00000000>, + <0x0000040 0x00000000>, + <0x0000044 0x00000000>, + <0x0000048 0x0000ffff>, + <0x000004c 0x00000000>; + u-boot,dm-pre-reloc; + }; + + soc_noc_fw_ddr_fpga2sdram_inst_2_ddr_scr@f8020400 { + reg = <0xf8020400 0x00000050>; + intel,offset-settings = + <0x0000000 0x00000000>, + <0x0000004 0x00000000>, + <0x0000008 0x00000000>, + <0x0000010 0x00000000>, + <0x0000014 0x00000000>, + <0x0000018 0x0000ffff>, + <0x000001c 0x00000000>, + <0x0000020 0x00000000>, + <0x0000024 0x00000000>, + <0x0000028 0x0000ffff>, + <0x000002c 0x00000000>, + <0x0000030 0x00000000>, + <0x0000034 0x00000000>, + <0x0000038 0x0000ffff>, + <0x000003c 0x00000000>, + <0x0000040 0x00000000>, + <0x0000044 0x00000000>, + <0x0000048 0x0000ffff>, + <0x000004c 0x00000000>; + u-boot,dm-pre-reloc; + }; }; |