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| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2022-03-01 11:50:51 +0800 |
|---|---|---|
| committer | Lokanathan, Raaj <raaj.lokanathan@intel.com> | 2022-06-14 19:01:58 +0800 |
| commit | 98fa952b063c371e4238b86e9df9cb0b2a64560e (patch) | |
| tree | 7947ab519276414e48b77438ea85fa6d25e431c6 | |
| parent | 241848812358535885df315899c5c4b72dce0315 (diff) | |
| download | u-boot-socfpga-98fa952b063c371e4238b86e9df9cb0b2a64560e.tar.gz | |
HSD #18020445323-9: arm: dts: agilex: Add ccu_mem0_I_main QoS
Adding example of ccu_mem0_I_main QoS settings with default reset
value in DTS for the sake of easy reference by user.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| -rw-r--r-- | arch/arm/dts/socfpga_agilex-u-boot.dtsi | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi index f89a755134..3efb108660 100644 --- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi @@ -127,6 +127,24 @@ <0x000004c 0x00000000>; u-boot,dm-pre-reloc; }; + + /* + * Example of ccu_mem0_I_main QOS settings with + * default reset value for the sake of easy reference + * by users. Users may choose to remove any of these register + * configurations that they do not require in their specific + * implementation. + */ + soc_mpfe_noc_inst_0_ccu_mem0_I_main_QosGenerator@f8022080 { + reg = <0xf8022080 0x0000001c>; + intel,offset-settings = + <0x0000008 0x80000200>, + <0x000000c 0x00000003>, + <0x0000010 0x00000BFE>, + <0x0000014 0x00000008>, + <0x0000018 0x00000000>; + u-boot,dm-pre-reloc; + }; }; &sysmgr { |