diff options
| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2022-04-07 17:25:04 +0800 |
|---|---|---|
| committer | Lokanathan, Raaj <raaj.lokanathan@intel.com> | 2022-06-14 19:01:58 +0800 |
| commit | 9cee17313ab30b71dc53a98035c2ce3c3e883de0 (patch) | |
| tree | 0f69d9e7ef3c7871f0707d46ff62a3ec79a9943b | |
| parent | aff63ee7da9c07920fcb12aee7456ea3ae05d081 (diff) | |
| download | u-boot-socfpga-9cee17313ab30b71dc53a98035c2ce3c3e883de0.tar.gz | |
HSD #15010938416: arm: dts: soc64: changing DDR aliasing addresses
The benefit of using these recommended aliasing addresses is the base
address of DDR is always same regardless DDR size change.
This would be easier for other master which sharing the same DDR with
MPU using the same DDR aliasing addresses without impacted by the DDR
size change. The changes only applied to Intel own DDR design such as
Stratix 10 and Agilex.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| -rw-r--r-- | arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 26 | ||||
| -rwxr-xr-x | arch/arm/dts/socfpga_stratix10_socdk.dts | 26 | ||||
| -rw-r--r-- | arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi | 26 |
3 files changed, 70 insertions, 8 deletions
diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 6efe2f0952..8d50271b49 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> */ #include "socfpga_agilex-u-boot.dtsi" @@ -28,9 +28,29 @@ }; memory { - /* 8GB */ + /* + * Recommended Aliasing addresses + * + * 16GB + * <0 0x00000000 0 0x80000000>, + * <0x10 0x80000000 3 0x80000000>; + * + * 8GB + * <0 0x00000000 0 0x80000000>, + * <0x10 0x80000000 1 0x80000000>; + * + * 4GB + * <0 0x00000000 0 0x80000000>, + * <0x10 0x80000000 0 0x80000000>; + * + * 2GB + * <0 0x00000000 0 0x80000000>; + * + * Note: Need to set CONFIG_NR_DRAM_BANKS=1 for 2GB in defconfig + * Default CONFIG_NR_DRAM_BANKS=2 is used for other DDR size + */ reg = <0 0x00000000 0 0x80000000>, - <2 0x80000000 1 0x80000000>; + <0x10 0x80000000 1 0x80000000>; }; }; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index 6bffd07032..237461f943 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2018 Intel Corporation + * Copyright (C) 2018-2022 Intel Corporation */ #include "socfpga_stratix10.dtsi" @@ -36,9 +36,29 @@ #address-cells = <2>; #size-cells = <2>; device_type = "memory"; - /* 4GB */ + /* + * Recommended Aliasing addresses + * + * 16GB + * <0 0x00000000 0 0x80000000>, + * <0x10 0x80000000 3 0x80000000>; + * + * 8GB + * <0 0x00000000 0 0x80000000>, + * <0x10 0x80000000 1 0x80000000>; + * + * 4GB + * <0 0x00000000 0 0x80000000>, + * <0x10 0x80000000 0 0x80000000>; + * + * 2GB + * <0 0x00000000 0 0x80000000>; + * + * Note: Need to set CONFIG_NR_DRAM_BANKS=1 for 2GB in defconfig + * Default CONFIG_NR_DRAM_BANKS=2 is used for other DDR size + */ reg = <0 0x00000000 0 0x80000000>, - <1 0x80000000 0 0x80000000>; + <0x10 0x80000000 0 0x80000000>; u-boot,dm-pre-reloc; }; }; diff --git a/arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi index ae859ab42e..7797238e7c 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright Altera Corporation (C) 2020. All rights reserved. + * + * Copyright (C) 2022 Intel Corporation */ #include "socfpga_stratix10_socdk-u-boot.dtsi" @@ -10,9 +12,29 @@ #address-cells = <2>; #size-cells = <2>; device_type = "memory"; - /* 4GB */ + /* + * Recommended Aliasing addresses + * + * 16GB + * <0 0x00000000 0 0x80000000>, + * <0x10 0x80000000 3 0x80000000>; + * + * 8GB + * <0 0x00000000 0 0x80000000>, + * <0x10 0x80000000 1 0x80000000>; + * + * 4GB + * <0 0x00000000 0 0x80000000>, + * <0x10 0x80000000 0 0x80000000>; + * + * 2GB + * <0 0x00000000 0 0x80000000>; + * + * Note: Need to set CONFIG_NR_DRAM_BANKS=1 for 2GB in defconfig + * Default CONFIG_NR_DRAM_BANKS=2 is used for other DDR size + */ reg = <0 0x00000000 0 0x80000000>, - <1 0x80000000 0 0x80000000>; + <0x10 0x80000000 0 0x80000000>; u-boot,dm-pre-reloc; }; |