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authorTien Fong Chee <tien.fong.chee@intel.com>2022-03-28 17:14:17 +0800
committerLokanathan, Raaj <raaj.lokanathan@intel.com>2022-06-14 19:01:58 +0800
commitf319e2be90bb182e82b1c536741a11997fec511a (patch)
tree72963d35dd46435df7a6ece77258b07908509699
parent5802807e0dfb7aaae78ca84e62274b8664abc872 (diff)
downloadu-boot-socfpga-f319e2be90bb182e82b1c536741a11997fec511a.tar.gz
HSD #18020445323-6: arm: dts: s10: Move CCU config of OCRAM to DTS
Centralizing S10 CCU config of OCRAM related accesses in DTS. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
-rw-r--r--arch/arm/dts/socfpga_stratix10-u-boot.dtsi4
-rw-r--r--arch/arm/mach-socfpga/spl_s10.c6
2 files changed, 4 insertions, 6 deletions
diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
index 8acfef280d..ed844c0080 100644
--- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
@@ -23,6 +23,10 @@
<0x0004640 0x00000000>,
<0x0004660 0x00000000>,
+ /* Disable ocram security at CCU for non secure access */
+ <0x0004688 0xfffc0000>,
+ <0x0018628 0xfffc0000>,
+
/* Enable access to DDR region from IO master */
<0x00018560 0x00000000>,
<0x00018580 0x00000000>,
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index a7de815ee0..142e10220e 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -78,12 +78,6 @@ void board_init_f(ulong dummy)
hang();
}
- /* disable ocram security at CCU for non secure access */
- clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
- CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
- CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
-
#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {