diff options
| author | Chin Liang See <clsee@altera.com> | 2016-09-26 17:50:10 +0800 |
|---|---|---|
| committer | Chin Liang See <clsee@altera.com> | 2016-09-26 17:50:10 +0800 |
| commit | 95ab599e1ad7840e08be0aa567eea3fca357572f (patch) | |
| tree | c2fb93c9523a2ed2b45b9c142755f6c3769769f8 /arch/arm/include/asm | |
| parent | f5cd6b9becaee79161edda315cde6ffe67b9677e (diff) | |
| download | u-boot-socfpga-95ab599e1ad7840e08be0aa567eea3fca357572f.tar.gz | |
FogBugz #385884: Configuring SDRAM extra cycles on timing parametersrel_socfpga_v2013.01.01_17.06.02_prrel_socfpga_v2013.01.01_17.06.01_prrel_socfpga_v2013.01.01_17.05.02_prrel_socfpga_v2013.01.01_17.05.01_prrel_socfpga_v2013.01.01_17.04.02_prrel_socfpga_v2013.01.01_17.04.01_prrel_socfpga_v2013.01.01_17.03.01_prrel_socfpga_v2013.01.01_17.02.01_prrel_socfpga_v2013.01.01_16.10.02_prrel_socfpga_v2013.01.01_16.10.01_prACDS17.0_REL_GSRD_RC1ACDS17.0_REL_GSRD_PRACDS16.1_REL_GSRD_RC7ACDS16.1_REL_GSRD_RC6ACDS16.1_REL_GSRD_RC5ACDS16.1_REL_GSRD_RC4ACDS16.1_REL_GSRD_PR
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface
Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes in v2
- Remove the change of handoff as our dev kit using DDR3
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-socfpga/sdram.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-socfpga/sdram.h b/arch/arm/include/asm/arch-socfpga/sdram.h index ca69ba01e9..7067f59db4 100644 --- a/arch/arm/include/asm/arch-socfpga/sdram.h +++ b/arch/arm/include/asm/arch-socfpga/sdram.h @@ -73,6 +73,8 @@ void sdram_ecc_init(void); #define SDR_CTRLGRP_LOWPWRTIMING_ADDRESS 0x5014 /* Register: sdr.ctrlgrp.dramodt */ #define SDR_CTRLGRP_DRAMODT_ADDRESS 0x5018 +/* Register: sdr.ctrlgrp.extratime1 */ +#define SDR_CTRLGRP_EXTRATIME1_ADDRESS 0x501C /* Register: sdr.ctrlgrp.dramaddrw */ #define SDR_CTRLGRP_DRAMADDRW_ADDRESS 0x502c /* Register: sdr.ctrlgrp.dramifwidth */ @@ -449,6 +451,13 @@ SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \ /* Field instance: sdr::ctrlgrp::dramsts */ #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004 +/* Register template: sdr::ctrlgrp::extratime1 */ +#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20 +#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_MASK 0x00f00000 +#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24 +#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_MASK 0x0f000000 +#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28 +#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_MASK 0xf0000000 /* To determine the duration of SDRAM test */ /* quick test which run around 5s */ |