FogBugz #158674: Enabling I2C support for U-Boot

Enable the DesignWare I2C controller support within U-Boot.
Only I2C0 is enabled per Cyclone V and Arria V dev kit. At
same time, rename socfpga_base_addrs.h to hardware.h. This is
to align with the file name used by DesignWare I2C driver.

Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v4
- Update the license header for hardware.h
Changes for v3
- Renamed socfpga_base_addrs.h to hardware.h
Changes for v2
- Updated hardware.h which mainly used for I2C driver

3 files changed, 11 insertions, 10 deletions

diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index 050805c71e..c68734d64d 100644
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -39,7 +39,7 @@
 	CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
 	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
 
-unsigned long cm_uart_clock;
+unsigned long cm_l4_sp_clock;
 unsigned long cm_sdmmc_clock;
 unsigned long cm_qspi_clock;
 
@@ -494,7 +494,7 @@ unsigned long cm_get_sdram_clk_hz(void)
 	return clock;
 }
 
-unsigned long cm_get_uart_clk_hz(void)
+unsigned long cm_get_l4_sp_clk_hz(void)
 {
 	uint32_t reg, clock = 0;
 
@@ -665,7 +665,7 @@ void cm_print_clock_quick_summary(void)
 	printf("CLOCK: DDR clock %ld MHz\n",
 			(cm_get_sdram_clk_hz() / 1000000));
 	printf("CLOCK: UART clock %ld KHz\n",
-			(cm_get_uart_clk_hz() / 1000));
+			(cm_get_l4_sp_clk_hz() / 1000));
 	printf("CLOCK: MMC clock %ld KHz\n",
 			(cm_get_mmc_controller_clk_hz() / 1000));
 	printf("CLOCK: QSPI clock %ld KHz\n",
@@ -674,7 +674,7 @@ void cm_print_clock_quick_summary(void)
 
 void cm_derive_clocks_for_drivers(void)
 {
-	cm_uart_clock = cm_get_uart_clk_hz();
+	cm_l4_sp_clock = cm_get_l4_sp_clk_hz();
 	cm_sdmmc_clock = cm_get_mmc_controller_clk_hz();
 	cm_qspi_clock = cm_get_qspi_controller_clk_hz();
 }
diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h
index 445a4d4b95..eaf4c27ace 100644
--- a/arch/arm/include/asm/arch-socfpga/clock_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h
@@ -59,7 +59,7 @@ typedef struct {
 extern int cm_basic_init(const cm_config_t *cfg);
 unsigned long cm_get_mpu_clk_hz(void);
 unsigned long cm_get_sdram_clk_hz(void);
-unsigned long cm_get_uart_clk_hz(void);
+unsigned long cm_get_l4_sp_clk_hz(void);
 unsigned long cm_get_mmc_controller_clk_hz(void);
 unsigned long cm_get_qspi_controller_clk_hz(void);
 void cm_print_clock_quick_summary(void);
@@ -252,7 +252,7 @@ void cm_derive_clocks_for_drivers(void);
 #define CLKMGR_QSPI_CLK_SRC_PER		0x2
 
 /* global variable which consume by drivers */
-extern unsigned long cm_uart_clock;
+extern unsigned long cm_l4_sp_clock;
 extern unsigned long cm_sdmmc_clock;
 extern unsigned long cm_qspi_clock;
 
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/hardware.h
index 2470ebd773..26f657797b 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/hardware.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2012-2014 Altera Corporation <www.altera.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -15,8 +15,8 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef _SOCFPGA_BASE_ADDRS_H_
-#define _SOCFPGA_BASE_ADDRS_H_
+#ifndef _HARDWARE_H_
+#define _HARDWARE_H_
 
 #define SOCFPGA_EMAC0_ADDRESS 0xff700000
 #define SOCFPGA_EMAC1_ADDRESS 0xff702000
@@ -29,6 +29,7 @@
 #define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000
 #define SOCFPGA_UART0_ADDRESS 0xffc02000
 #define SOCFPGA_UART1_ADDRESS 0xffc03000
+#define SOCFPGA_I2C0_ADDRESS 0xffc04000
 #define SOCFPGA_SDR_ADDRESS 0xffc20000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
 #define SOCFPGA_L4WD0_ADDRESS 0xffd02000
@@ -43,4 +44,4 @@
 #define SOCFPGA_NAND_DATA_ADDRESS 0xff900000
 #define SOCFPGA_NAND_REGS_ADDRESS 0xffb80000
 
-#endif /* _SOCFPGA_BASE_ADDRS_H_ */
+#endif /* _HARDWARE_H_ */