ddr: altera: dm: Add SDRAM driver for Diamond Mesa

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

3 files changed, 74 insertions, 1 deletions

diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h
index a2face0570..06c941937b 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -121,6 +121,7 @@ struct socfpga_firwall_l4_sys {
 #define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT		0x1c
 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT		0x98
 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT	0x9c
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD	0xff
 
 /* Firewall MPFE SCR Registers */
 #define FW_MPFE_SCR_HMC					0x00
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 130d156473..c19fa3889b 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -47,6 +47,10 @@ int qspi_flash_software_reset(void);
 int is_fpga_config_ready(void);
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_DM)
+bool is_ddr_init_skipped(void);
+#endif
+
 void do_bridge_reset(int enable, unsigned int mask);
 void socfpga_pl310_clear(void);
 void socfpga_get_managers_addr(void);
diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c
index 8330ef6e12..6fc6840f6a 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2020 Intel Corporation <www.intel.com>
  *
  */
 
@@ -20,6 +20,14 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Reset type */
+enum reset_type {
+	por_reset,
+	warm_reset,
+	cold_reset,
+	rsu_reset
+};
+
 /*
  * FPGA programming support for SoC FPGA Stratix 10
  */
@@ -100,3 +108,63 @@ void arch_preboot_os(void)
 {
 	mbox_hps_stage_notify(HPS_EXECUTION_STATE_OS);
 }
+
+/* Only applicable to DM */
+#ifdef CONFIG_TARGET_SOCFPGA_DM
+static bool is_ddr_retention_enabled(u32 boot_scratch_cold0_reg)
+{
+	return boot_scratch_cold0_reg &
+	       ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK;
+}
+
+static bool is_ddr_bitstream_sha_matching(u32 boot_scratch_cold0_reg)
+{
+	return boot_scratch_cold0_reg & ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK;
+}
+
+static enum reset_type get_reset_type(u32 boot_scratch_cold0_reg)
+{
+	return (boot_scratch_cold0_reg &
+		ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK) >>
+		ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT;
+}
+
+bool is_ddr_init_skipped(void)
+{
+	u32 reg = readl(socfpga_get_sysmgr_addr() +
+			SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+
+	if (get_reset_type(reg) == por_reset) {
+		debug("%s: POR reset is triggered\n", __func__);
+		debug("%s: DDR init is required\n", __func__);
+		return false;
+	}
+
+	if (get_reset_type(reg) == warm_reset) {
+		debug("%s: Warm reset is triggered\n", __func__);
+		debug("%s: DDR init is skipped\n", __func__);
+		return true;
+	}
+
+	if ((get_reset_type(reg) == cold_reset) ||
+	    (get_reset_type(reg) == rsu_reset)) {
+		debug("%s: Cold/RSU reset is triggered\n", __func__);
+
+		if (is_ddr_retention_enabled(reg)) {
+			debug("%s: DDR retention bit is set\n", __func__);
+
+			if (is_ddr_bitstream_sha_matching(reg)) {
+				debug("%s: Matching in DDR bistream\n",
+				      __func__);
+				debug("%s: DDR init is skipped\n", __func__);
+				return true;
+			}
+
+			debug("%s: Mismatch in DDR bistream\n", __func__);
+		}
+	}
+
+	debug("%s: DDR init is required\n", __func__);
+	return false;
+}
+#endif