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authorChee Hong Ang <chee.hong.ang@intel.com>2017-11-07 01:41:06 -0800
committerChee Hong Ang <chee.hong.ang@intel.com>2017-11-13 22:04:38 -0800
commit04d5048232cedf8aac2d57c343243317aea9aef8 (patch)
tree61ebc835d3e3a6b896a9c29e1018ddcbc855aed1 /configs
parent4b99b56bb897e942cd74fbeec5164a9f3f460143 (diff)
downloadu-boot-socfpga-04d5048232cedf8aac2d57c343243317aea9aef8.tar.gz
FogBugz #506599: Add Stratix10 FPGA reconfiguration support
FPGA reconfiguration support through Secure Device Manager's mailbox. User is required to program the bitstream into the QSPI flash. Then use "fpga load" command with bitstream location address in QSPI to start the FPGA reconfiguration process. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Diffstat (limited to 'configs')
-rwxr-xr-xconfigs/socfpga_stratix10_defconfig3
1 files changed, 3 insertions, 0 deletions
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index af17ce1ed3..5a1cc61788 100755
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -43,3 +43,6 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_HUSH_PARSER=y
+CONFIG_FPGA_ALTERA=y
+CONFIG_FPGA_STRATIX10=y
+