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| author | Siew Chin Lim <elly.siew.chin.lim@intel.com> | 2020-09-08 15:55:03 +0800 |
|---|---|---|
| committer | Yau Wai Gan <yau.wai.gan@.intel.com> | 2020-10-27 14:40:34 +0800 |
| commit | cc42d9d0175f50ace811ae45ded12aca7a9811ec (patch) | |
| tree | bc568b22361036578422150d53cf1fc409b505ea /scripts/Makefile.spl | |
| parent | 4b17bc83373012589df694112a6e1be5daf231f1 (diff) | |
| download | u-boot-socfpga-cc42d9d0175f50ace811ae45ded12aca7a9811ec.tar.gz | |
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Diffstat (limited to 'scripts/Makefile.spl')
| -rw-r--r-- | scripts/Makefile.spl | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 67d05aa043..5a6901d78f 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -223,8 +223,7 @@ ifneq ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),) INPUTS-y += $(obj)/$(SPL_BIN).sfp endif -ALL-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/u-boot-spl-dtb.hex -ALL-$(CONFIG_TARGET_SOCFPGA_AGILEX) += $(obj)/u-boot-spl-dtb.hex +INPUTS-$(CONFIG_TARGET_SOCFPGA_SOC64) += $(obj)/u-boot-spl-dtb.hex ifdef CONFIG_ARCH_SUNXI INPUTS-y += $(obj)/sunxi-spl.bin |