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* FogBugz #504009: arm: socfpga: stratix10: Enable PSCI system resetChin Liang See2017-12-213-0/+27
| | | | | | | Enable psci_system_reset support for Stratix10. This PSCI function will eventually trigger the mailbox HPS_REBOOT to SDM. Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* FogBugz #504008: arm: socfpga: stratix10: Ensure mailbox is PSCI compatibleChin Liang See2017-12-212-31/+43
| | | | | | | | | | | Re-factor the Stratix10 mailbox driver to be compatible with PSCI. Delay or printf will be removed since PSCI code today doesn't support UART and timer. All mailbox function shall be inlined to ensure it will stick together with PSCI functions which will be located to OCRAM. Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* FogBugz #503969: arm: socfpga: stratix10: Enable PSCI supportChin Liang See2017-12-212-0/+12
| | | | | | | Enable the PSCI support in Stratix10. The PSCI code will support 4 CPUs and reside at on-chip RAM. Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* FogBugz #503967: arm: Disable fwcall when PSCI is enabledChin Liang See2017-12-211-0/+2
| | | | | | | | When PSCI is enabled, we are expecting U-Boot which now act as EL3 software will handle all the PSCI calls. We won't need fwcall as no further HVC or SMC are needed. Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* FogBugz #513999-2: arm: socfpga: stratix10: Enable i2c supportChin Liang See2017-12-183-1/+16
| | | | | | Enable i2c support for SOCFPGA Stratix10 SoC dev kit. Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* FogBugz #513999-1: arm: dts: stratix10: Enable i2c supportChin Liang See2017-12-181-0/+10
| | | | | | Added i2c node for SOCFPGA Stratix10 SoC dev kit. Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* FogBugz #511271: arm: socfpga: stratix10: Remove hard code of clock source ↵Chin Liang See2017-12-182-3/+17
| | | | | | | | | frequency To fix the clock driver to grab the clock source frequency from handoff binary blob. Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* FogBugz #506764: arm: socfpga: stratix10: Fix VCO algorithmChin Liang See2017-12-181-2/+2
| | | | | | | Fix the algorithm which calculates the VCO mscnt value. When the refclkdiv is not 1, the PLL is not able to lock without this fix. Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* FogBugz #520012: mailbox: stratix10: Mailbox Initializationrel_socfpga_v2017.09_17.12.01_prACDS18.0IR1_REL_S10_GSRD_EAPThor Thayer2017-12-121-0/+6
| | | | | | | | | | | U-Boot/SPL and SDM firmware use the doorbells to indicate data is available in the mailbox. The doorbell from SDM is cleared by SPL during transactions. Ensure the doorbell is cleared on initialization. Ensure the urgent request register is in the initialized state (cleared). Signed-off-by: Thor Thayer <thor.thayer@intel.com>
* FogBugz #517510: mailbox: stratix10: Check for Urgent ACK toggleThor Thayer2017-12-081-3/+6
| | | | | | | | U-Boot/SPL and firmware have a handshake sequence for the urgent request. This patch checks the Urgent ACK for a toggle as specified in the documentation instead of a bit set. Signed-off-by: Thor Thayer <thor.thayer@intel.com>
* FogBugz #507879-3: arm: stratix10: Enable Linux QSPI controller supportrel_socfpga_v2017.09_17.11.02_prChin Liang See2017-11-162-2/+13
| | | | | | | | U-Boot will enable Linux QSPI controller support through updating the Linux device tree blob. This include updating the QSPI controller reference clock. Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* FogBugz #507879-2: arm: stratix10: Removing hard code of QSPI reference clockChin Liang See2017-11-163-4/+26
| | | | | | | | Obtaining the QSPI reference clock from QSPI_DIRECT mailbox command. The QSPI reference clock is setup by SDM and this info need to be passed by SDM to HPS. Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* FogBugz #507879-1: arm: stratix10: Enable retry for QSPI_OPENChin Liang See2017-11-141-2/+11
| | | | | | | | Do retry the QSPI_OPEN command again if it's failing for first time. This is to overcome scenario where HPS didn't properly issue QSPI_CLOSE during previous reset or reloading of HPS software. Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* FogBugz #506599: Add Stratix10 FPGA reconfiguration supportChee Hong Ang2017-11-138-1/+234
| | | | | | | | | FPGA reconfiguration support through Secure Device Manager's mailbox. User is required to program the bitstream into the QSPI flash. Then use "fpga load" command with bitstream location address in QSPI to start the FPGA reconfiguration process. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* FogBugz #507880: arm: stratix10: Enable HUSH parserChin Liang See2017-11-131-0/+1
| | | | | | | | Enable command line interpreter in Stratix10 SoC U-Boot in order to support more powerful command line syntax such as if...else...fi Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* FogBugz #503965: arm: stratix10: Enable HPS reboot supportChin Liang See2017-11-134-3/+27
| | | | | | | | | | | | | | | | | | Enable HPS reboot support in Stratix 10 SoC. Hard Processor System (HPS) only can initiate reboot by sending mailbox command to Secure Device Manager (SDM) Signed-off-by: Chin Liang See <chin.liang.see@intel.com> — Changes for v5 - Update the commit message Changes for v4 - Always return 0 if mailbox successfully sent Changes for v3 - Added more clarity to comments - Fixed a change that break CV build Changes for v2 - Put processor into while loop and wait for watchdog when mailbox failed
* FogBugz #510027: Enable USB on Stratix10 platformDinh Nguyen2017-11-093-0/+25
| | | | | | | | Add USB functionality on the Stratix10 devkit. This includes adding the USB DTS entry, de-assert the USB and USB_OCP reset bits, add the USB command support to defconfig. Signed-off-by: Dinh Nguyen <dinh.nguyen@intel.com>
* FogBugz #507927: nand_data bit is in peripheral firewall baserel_socfpga_v2017.09_17.11.01_prDinh Nguyen2017-11-021-1/+1
| | | | | | | Fix up the firewall disable bit for the nand_data register. The bit lives in the firewall peripheral base, not the firewall system base. Signed-off-by: Dinh Nguyen <dinh.nguyen@intel.com>
* FogBugz #505813: remove unnecessary reset de-assertsDinh Nguyen2017-10-311-3/+1
| | | | | | | | | Now that the reset manager for Stratix 10 is working in Linux, we don't need the bootloader to bring the peripherals out of reset. Signed-off-by: Dinh Nguyen <dinh.nguyen@intel.com> --- v2: need to bring out sdmmc for SPL
* FogBugz #505560: Enable non-secure access to all HPS peripheralsDinh Nguyen2017-10-311-26/+37
| | | | | | | | | Most OS are running in EL2 or lower, so by default an access to a HPS peripheral is done with a non-secure method, which causes a system error exception. Thus, the bootloader should enable non-secure access to all peripherals, including clock/reset/system managers. Signed-off-by: Dinh Nguyen <dinh.nguyen@intel.com>
* FogBugz #490494-3: enable non-secure PL330 peripheralsGraham Moore2017-10-242-1/+4
| | | | | | | This patch configures the PL330 DMAC peripheral request lines in non-secure mode via the system manager registers. Signed-off-by: Graham Moore <graham.moore@linux.intel.com>
* FogBugz #490494-2: take PL330 DMAC out of resetGraham Moore2017-10-241-0/+2
| | | | | | | | | Normally, Linux would take the PL330 DMAC out of reset, but because the PL330 is a "primecell" device, Linux tries to probe its configuration space for a device id, which causes a hang if the DMAC is still in reset. This patch takes the PL330 out of reset. Signed-off-by: Graham Moore <graham.moore@linux.intel.com>
* FogBugz #490494-1: enable non-secure PL330 interfaceGraham Moore2017-10-242-0/+8
| | | | | | | This patch configures the PL330 DMAC in non-secure mode via the system manager registers. Signed-off-by: Graham Moore <graham.moore@linux.intel.com>
* arm: socfpga: stratix10: Move QSPI U-Boot Image Locationrel_socfpga_v2017.09_17.10.02_prrel_socfpga_v2017.09_17.10.01_prThor Thayer2017-10-091-1/+1
| | | | | | | | | | | | | | | Move expected image of U-Boot QSPI image to the end of the first partition (0 to 0x400_0000) to allow room for FPGA programming image. 1. The complete partition is from 0 to 0x400_0000 for the 1Gb QSPI size. This may change for 2Gb QSPI. 2. The FPGA-first image will be from 0 to 0x3C0_0000 3. The U-Boot image will be from 0x3C0_0000 to 0x400_0000 4. This is an interim solution for U-Boot in the raw partition. In the future, it is planned to move U-Boot inside the 2nd partition where the filesystem/etc resides. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
* arm: stratix10: enable non-secure access to GPIOsDinh Nguyen2017-10-091-0/+4
| | | | | | Enables non-secure access to gpio0 and gpio1. Signed-off-by: Dinh Nguyen <dinh.nguyen@intel.com>
* arm: stratix10: enable non-secure access to USBDinh Nguyen2017-10-091-0/+4
| | | | | | Enables non-secure access to USB0 and USB1. Signed-off-by: Dinh Nguyen <dinh.nguyen@intel.com>
* arm: stratix10: enable non-secure access to reset managerDinh Nguyen2017-10-091-0/+3
| | | | | | | Non-secure OS needs access to the reset manager register in order to bring peripherals out of reset. Signed-off-by: Dinh Nguyen <dinh.nguyen@intel.com>
* spi: cadence_qspi: Fix the indirect trigger addressrel_socfpga_v2017.09_17.09.03_prrel_socfpga_v2017.09_17.09.02_prChin Liang See2017-09-181-4/+2
| | | | | | | | The indirect trigger address is actually using offset instead of the address of ahbbase. It was working well in CV and A10 as there is a hardware masking on the lower bits of the value Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* arm64: Ensure relocated spin table address is updated back to SPLChin Liang See2017-09-181-0/+4
| | | | | | | | When SPL is used as EL3, SPL will trap other processors than CPU0 into spin loop. When U-Boot updated the spin table address after U-Boot relocate, we want to ensure the CPU_RELEASE_ADDR is updated. Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* arm: socfpga: stratix10: Enable Stratix10 SoC buildChin Liang See2017-09-184-3/+273
| | | | | | Add build support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* board: altera: stratix10: Add socdk board support for Stratix10 SoCChin Liang See2017-09-183-0/+21
| | | | | | Add socdk board support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* ddr: altera: stratix10: Add DDR support for Stratix10 SoCChin Liang See2017-09-183-0/+716
| | | | | | Add DDR support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* arm: socfpga: stratix10: Add timer support for Stratix10 SoCChin Liang See2017-09-181-1/+16
| | | | | | Add timer support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* arm: socfpga: stratix10: Add SPL driver for Stratix10 SoCChin Liang See2017-09-184-0/+230
| | | | | | Add SPL driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* arm: socfpga: Restructure the SPL fileChin Liang See2017-09-184-235/+219
| | | | | | | | Restructure the SPL so each devices such as CV, A10 and S10 will have their own dedicated SPL file. SPL file determine the HW initialization flow which is device specific Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* arm: socfpga: stratix10: Add MMU support for Stratix10 SoCChin Liang See2017-09-182-0/+72
| | | | | | Add MMU support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* arm: socfpga: stratix10: Add mailbox support for Stratix10 SoCChin Liang See2017-09-183-0/+342
| | | | | | Add mailbox support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* arm: socfpga: stratix10: Add misc support for Stratix10 SoCChin Liang See2017-09-183-0/+170
| | | | | | Add misc support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* arm: socfpga: stratix10: Add pinmux support for Stratix10 SoCChin Liang See2017-09-185-1/+316
| | | | | | Add pinmux driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoCChin Liang See2017-09-186-0/+361
| | | | | | Add Reset Manager driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoCChin Liang See2017-09-187-2/+644
| | | | | | Add Clock Manager driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* arm: dts: Add dts for Stratix10 SoCChin Liang See2017-09-182-1/+143
| | | | | | Device tree for Stratix10 SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* arm: socfpga: stratix10: Add base address map for Statix10 SoCChin Liang See2017-09-181-0/+58
| | | | | | Add the base address map for Statix10 SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
* Prepare v2017.09v2017.09Tom Rini2017-09-111-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* MAINTAINERS: board: qcom: db410c: Maintainer changedJorge Ramirez-Ortiz2017-09-111-1/+1
| | | | | | | Replacing original author Mateusz Kulikowski <mateusz.kulikowski@gmail.com> as db410c maintainer Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
* cmd: ide: Make the first device the default oneBin Meng2017-09-101-1/+1
| | | | | | | | | | | At present the IDE device number is initialized to -1, which means we cannot type "ide read" command before setting the device number via "ide device #". For convenience, let's set the first device as the default one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* block: ide: Don't bother to create BLK device if no CDROM insertedBin Meng2017-09-101-0/+7
| | | | | | | | When there is no CDROM inserted, the block size is zero hence there is no need to create a BLK device for it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* block: ide: Fix block read/write with driver modelBin Meng2017-09-103-1/+75
| | | | | | | | | | | This converts the IDE driver to driver model so that block read and write are fully functional. Fixes: b7c6baef ("x86: Convert MMC to driver model") Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* blk: Use macros for block device vendor/product/rev string sizeBin Meng2017-09-101-3/+7
| | | | | | | So far these are using magic numbers. Replace them with macros. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* edison: Disable CONFIG_USB_HOST_ETHERTom Rini2017-09-081-0/+1
| | | | | | | This board does dwc3 gadget, not host, so we cannot have host support or we will fail to link. Signed-off-by: Tom Rini <trini@konsulko.com>
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