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* socfpga: readme: Update tested Intel Quartus version of Stratix 10rel_socfpga_v2020.04_21.05.01_prrel_socfpga_v2020.04_21.04.02_prrel_socfpga_v2020.04_21.04.01_prrel_socfpga_v2020.04_21.03.02_prrel_socfpga_v2020.04_21.03.01_prrel_socfpga_v2020.04_21.02.02_prrel_socfpga_v2020.04_21.02.01_prrel_socfpga_v2020.04_21.01.02_prrel_socfpga_v2020.04_21.01.01_prrel_socfpga_v2020.04_20.12.03_prsocfpga_v2020.04Siew Chin Lim2020-12-081-1/+1
| | | | | | | Tested Stratix 10 with Intel Quartus Prime Pro Edition 19.3 and 19.4 versions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* socfpga: readme: Agilex does not support VABrel_socfpga_v2020.04_20.12.02_prSiew Chin Lim2020-11-201-1/+1
| | | | | | | | Fix error in "Software Feature" table: Agilex does not support Vendor Authorized Boot (VAB) in socfpga_v2020.04 branch. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* socfpga: readme: Restructure content of Intel socfpga readme filerel_socfpga_v2020.04_20.12.01_prrel_socfpga_v2020.04_20.11.02_prSiew Chin Lim2020-11-111-124/+191
| | | | | | | | | | | | | Rewrite the readme file to provide an overview of Intel U-Boot supports. 3 new sections have been added into the readme file: 1. Device Family Support vs Tested Intel Quartus 2. Feature Support 3. Major Changes and Known Issues Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* HSD #16012019972: fpga: intel_sdm_mb: Add checking for INTEL_SIP_SMC_STATUS_BUSYLey Foon Tan2020-11-061-1/+2
| | | | | | | | | | Add checking for INTEL_SIP_SMC_STATUS_BUSY (1). Status busy means transfer is accepted but SDM does not have more freed buffer. It is not an error. Continue process the data if receive OK and BUSY status. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* HSD #1508499730: rsu: call 'rsu dtb' before boot LinuxSiew Chin Lim2020-11-041-1/+1
| | | | | | | U-Boot to call 'rsu dtb' before boot to Linux to update Linux DTB qspi-boot parition offset with spt0 value. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* HSD: #1508430891: Revert: ddr: altera: soc64: Add secure region supportrel_socfpga_v2020.04_20.11.01_prLey Foon Tan2020-10-226-66/+41
| | | | | | | | | This reverts commit 04e0e572a395ecae8224413188a10b06a97d1ff9. This cause SDMMC failed to load from SD card. Revert it first, before we found the solution. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* HSD: #1508430891: ddr: altera: soc64: Add secure region supportLey Foon Tan2020-10-206-41/+66
| | | | | | | | | | | | | | | Setting up firewall regions based on SDRAM memory banks configuration (up to CONFIG_NR_DRAM_BANKS banks) instead of using whole address space (including address hole). First 1 MiB (0 to 0xfffff) of SDRAM always set as secure region, other address spaces are non-secure region. ARM Trusted Firmware (ATF) image or SMC code is located in this first 1 MiB memory region. This is to prevent non-secure state EL1 and EL2 access to secure region. Add common function for firewall setup and reuse for all SoC64 devices. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* HSD #22010730357: rsu: additional changes to handle SPT/CPB saveRichard Gong2020-10-201-0/+7
| | | | | | | Save the size of saved SPT/CPB data to environment variable filesize, and output the saved data size messages. Signed-off-by: Richard Gong <richard.gong@intel.com>
* HSD #1508313350: Enable firewall to allow access to various componentsrel_socfpga_v2020.04_20.10.03_prTien Fong Chee2020-10-043-0/+33
| | | | | | | | | | | | Enable firewall to allow access to various components which are part of requirement for the features that needed to be supported in GHRD. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> --- v1->v2 - Removed redundancy code.
* net: tftp: Fix load_block offset calculationLey Foon Tan2020-10-021-1/+2
| | | | | | | | | | | | | | | [Upstream commit f6a158b996b3abee4e6315b29a488398cb3946df] When load the last block, the "len" might not be a block size. This cause loading the incorrect last block data. The fix change "len" to tftp_block_size and minus one tftp_block_size for offset calculation. Use same offset calculation formula as in store_block(). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
* net: tftp: Fix store_block offset calculationLey Foon Tan2020-10-021-2/+3
| | | | | | | | | | | | | | | [Upstream commit ae0bdf09ca9737d5db9453966cf4705bdd420d31] tftp_cur_block start with 1 for first block, but tftp_cur_block counter is start with zero when block number is rollover. The existing code "tftp_cur_block - 1" will cause the block number become -1 in store_block() when tftp_cur_block is 0 when tftp_cur_block is rollover. The fix pass in tftp_cur_block to store_block() and minus the tftp_block_size when do the offset calculation. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
* net: tftp: Fix tftp_prev_block counter updateLey Foon Tan2020-10-021-0/+1
| | | | | | | | | | | | | | | [Upstream commit 6bf46367f5f1fd159f8a497d094ecfcbb6bc3c1d] Fixes missing update to tftp_prev_block counter before increase tftp_cur_block counter when do the tftpput operation. tftp_prev_block counter is used in update_block_number() function to check whether block number (sequence number) is rollover. This bug cause the tftpput command fail to upload a large file when block number is greater than 16-bit (0xFFFF). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
* cache: l2x0: Fix missing write to Auxiliary Control Registerrel_socfpga_v2020.04_20.10.02_prLey Foon Tan2020-09-251-0/+2
| | | | | | | | | | | [Upstream ID 653f7c44677cd13bb106673bb7c46542e217fa13] In commit f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override bit") we removed writel to regs->pl310_aux_ctrl by accident. This commit restores it back. Fixes: f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override bit") Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* HSD #1508325891-2: tools: socfpgaimage: Add param entry point (ep) support ↵Ley Foon Tan2020-09-231-8/+13
| | | | | | | | | | | for Arria 10 (v1) Add param entry point (ep) support for Arria 10 header. User can pass in 'e' option to mkimage to set the entry point. This is an optional option. If not specified, default is 0x14. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* HSD #1508325891-1: tools: socfpgaimage: Add check params function for Arria ↵Ley Foon Tan2020-09-231-3/+26
| | | | | | | | | | | | | | | 10 (v1) Add check params function for Arria 10 (header v1). From [1] page 42, entry point offset should be 4 bytes aligned and any value smaller than 0x14 is invalid. Rename existing socfpgaimage_check_params() for v0. [1]: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_soc_eds.pdf Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: dm: Enable Intel Diamond Mesa bulidrel_socfpga_v2020.04_20.10.01_prSiew Chin Lim2020-09-175-2/+276
| | | | Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* configs: dm: Add Diamond Mesa CONFIGsSiew Chin Lim2020-09-171-0/+50
| | | | Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* arm: dts: dm: Add base dtsi and devkit dts for Diamond MesaSiew Chin Lim2020-09-175-0/+935
| | | | | Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* board: intel: dm: Add socdk board support for Diamond MesaSiew Chin Lim2020-09-173-0/+21
| | | | Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* arm: socfpga: dm: Add SPL for Diamond MesaSiew Chin Lim2020-09-171-0/+96
| | | | Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* ddr: altera: dm: Add SDRAM driver for Diamond MesaSiew Chin Lim2020-09-176-2/+1309
| | | | | Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* arm: socfpga: Changed misc_s10.c to misc_soc64.cSiew Chin Lim2020-09-172-2/+2
| | | | | | | Rename to common file name to used by all SOC64 devices. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* arm: socfpga: dm: Add clock manager for Diamond MesaSiew Chin Lim2020-09-173-0/+95
| | | | Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* arm: socfpga: Changed to store QSPI reference clock in kHzSiew Chin Lim2020-09-174-7/+46
| | | | | | | | | | | | | | Changed to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex. This patch is in preparation for Diamond Mesa SDRAM driver support. Reserved 4 bits for Diamond Mesa SDRAM driver, and there will be 28 bits to store QSPI reference clock. Due to limited bits, QSPI reference clock frequency is converted to kHz from Hz. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* arm: socfpga: Move Stratix10 and Agilex clock manager common codeSiew Chin Lim2020-09-175-13/+13
| | | | | | | Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* drivers: clk: dm: Add memory clock driver for Diamond MesaSiew Chin Lim2020-09-173-0/+216
| | | | | | | Add memory clock manager driver for Diamond Mesa. Provides clock initialization and enable functions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* drivers: clk: dm: Add clock driver for Diamond MesaSiew Chin Lim2020-09-175-1/+793
| | | | | | | Add clock manager driver for Diamond Mesa. Provides clock initialization and get_rate functions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* arm: socfpga: Add handoff data support for Diamond MesaSiew Chin Lim2020-09-172-29/+88
| | | | | | | | Diamond Mesa support both HPS handoff data and DDR handoff data. HPS handoff data support re-use Straix10 and Agilex code. DDR handoff data is newly introduced in Diamond Mesa. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* arm: socfpga: Restructure Stratix10 and Agilex handoff codeSiew Chin Lim2020-09-177-92/+161
| | | | | | | | | Restructure Stratix10 and Agilex handoff code. Rename _s10.c file to _soc64.c file. Move common code that parsing the handoff data to wrap_handoff_soc64.c, in preparation to support handoff for Diamond Mesa. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* arm: socfpga: Rename Stratix10 and Agilex handoff common macrosSiew Chin Lim2020-09-176-59/+59
| | | | | | | Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from S10_HANDOFF to SOC64_HANDOFF. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* arm: socfpga: dm: Add firewall support for Diamond MesaSiew Chin Lim2020-09-171-1/+1
| | | | Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* arm: socfpga: dm: Add base address for Intel Diamond MesaSiew Chin Lim2020-09-171-1/+1
| | | | | | | Reuse base_addr_s10.h for Diamond Mesa, the address is the same as Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64Siew Chin Lim2020-09-179-22/+20
| | | | | | Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* HSD #22010730357: rsu: changes for Sub-Partition Table (SPT) enhancementsRichard Gong2020-09-025-2/+399
| | | | | | | | | | | | | | | | | | | | | | | | Changes are including: 1). integrity check a). check SPT header fields b). check SPT data fields c). check bot SPTs if both are same 2). new command and RSU core extension to support a). rsu restore_spt <address> - restore a saved SPT from address b). rsu save_spt <address> - save SPT to address If one of SPTs is corrupted, update the corrupted SPT with the good one. If both SPTs are corrupted, all SPT related operations are blocked until user successfully run "rsu restore_spt <address>". Signed-off-by: Richard Gong <richard.gong@intel.com> --- v5: add HSD to commit title, update commit messages v4: update global variable spt after restore_spt_from_address(), add error check at rsu_save_spt(), other changes to address review comments v3: return with the standard error codes, use memcmp v2: add check for magic number to prevent user from accidentally restoring CPB
* HSD #22010730370: rsu: changes for Configuration Pointer Block (CPB) ↵Richard Gong2020-09-025-22/+462
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enhancements Changes are including: 1). integrity check a). check CPB header b). check CPB data fields c). check both CPBs if both are same 2) new commands and RSU core extension to support a). rsu create_empty_cpb - create the empty CPB from the scratch b). rsu restore_cpb <address> - restore a saved CPB from address c). rsu save_cpb <address> - save CPB to address If one of CPBs is corrupted, update the corrupted CPB with the good one. If both CPBs are corrupted, all CPB related operations are blocked until user successfully run "rsu create_empty_cpb <address>" or "rsu restore_cpb <address>". Signed-off-by: Richard Gong <richard.gong@intel.com> --- v5: add HSD to commit title, update commit messages, replace cpb_backup_offset with cpb_reserved v4: update global variables (cpb and cpb_slots) after restore_cpb_from_address() and empty_cpb(), add error check at rsu_save_cpb() v3: return with the standard error codes, use memcmp v2: add check for magic number to prevent user from accidentally restoring SPB
* HSD #1508277418: Enable ATF support for QSPI & NAND bootrel_socfpga_v2020.04_20.09.02_prChee Hong Ang2020-08-205-0/+327
| | | | | | | Add defconfigs with ATF support for QSPI and NAND boot on Stratix10 and Agilex platforms. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* HSD #1508259592: Skip 'linux_qspi_enable' command if QSPI is not enabledrel_socfpga_v2020.04_20.09.01_prChee Hong Ang2020-08-131-0/+2
| | | | | | | SSBL shall not run 'linux_qspi_enable' before booting kernel if QSPI is not enabled in configs. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* HSD: #1707269957: configs: socfpga: cyclone5: Add QSPI defconfigLey Foon Tan2020-08-101-0/+74
| | | | | | | Add Cyclone 5 SoC QSPI defconfig. This defconfig supports QSPI boot from SPL to Linux and ENV in QSPI flash. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* HSD #14011791668: check decision firmware integrityradu bacrau2020-08-077-1/+255
| | | | | | | Added support for detecting decision firmware corruptions from both command line and through the SMC handler. Signed-off-by: Radu Bacrau <radu.bacrau@intel.com>
* HSD #1508234389-2: Skip handoff data access in SSBLrel_socfpga_v2020.04_20.08.02_prChee Hong Ang2020-08-051-1/+2
| | | | | | | | SPL already setup the Clock Manager with the handoff data from OCRAM. When the Clock Manager's driver get probed again in SSBL, it shall skip the handoff data access in OCRAM. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* HSD #1508234389-1: SSBL shall not setup stack on OCRAMChee Hong Ang2020-08-051-0/+5
| | | | | | | Since SSBL is running in DRAM, it shall setup the stack in DRAM instead of OCRAM which is occupied by SPL and handoff data. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* Revert "HSD #1507967433: reset: socfpga: add assert before de-asserting ↵Joyce Ooi2020-08-041-2/+0
| | | | | | | | | | | peripheral resets" This reverts commit 3790fce5412f3dc1b678706f14adc5905b43f5d2. Asserting and de-asserting peripheral resets causes unknown effects when booting up to Linux. So, disable it for now. Signed-off-by: Joyce Ooi <joyce.ooi@intel.com>
* configs: socfpga: soc64: Disable CONFIG_PSCI_RESET in NAND defconfigsChee Hong Ang2020-08-022-0/+2
| | | | | | | U-Boot running at EL3 shall not call SMC/PSCI reset runtime services to perform cold/warm reset. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* HSD #1508201592: fpga: intel_pr: Change to use fdt_get_resource()Ley Foon Tan2020-07-241-4/+8
| | | | | | | | | | Change from fdtdec_get_addr() to fdt_get_resource(). fdtdec_get_addr() returns a 64-bit value, including base address and register size. Change to use fdt_get_resource() and get base address from struct fdt_resource. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* HSD #16011471759: Skip bridge disable/enable in ATFrel_socfpga_v2020.04_20.08.01_prChee Hong Ang2020-07-211-1/+2
| | | | | | | | | | In U-Boot + ATF, U-Boot calls the FPGA reconfiguration SMC runtime services provided by ATF to perform FPGA reconfiguration. U-Boot need to pass '1' to 'CONFIG_START' SMC service to ensure ATF skip the bridge disable/enable operations and let user perform the bridge disable/enable manually. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* configs: socfpga: add bootcmd for cyclone5Chang Rebecca Swee Fun2020-07-221-1/+1
| | | | | | Add command to cyclone5 CONFIG_BOOTCOMMAND to run fatscript Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
* HSD #1508168527-5: arm: dts: socfpga: arria10: Move to use generic handoff dtsiLey Foon Tan2020-07-217-1376/+297
| | | | | | | Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include the generated _handoff.h header file from qts-filter-a10.sh script. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* HSD #1508168527-4: arm: socfpga: arria10: Add handoff header for A10 SoCDK NANDLey Foon Tan2020-07-211-0/+305
| | | | | | | Add the qts-filter-a10.sh generated handoff header file for the Arria10 SoCDK NAND u-boot device tree. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* HSD #1508168527-3: arm: dts: socfpga: arria10: Add handoff header for A10 ↵Ley Foon Tan2020-07-211-0/+305
| | | | | | | | | SoCDK QSPI Add the qts-filter-a10.sh generated handoff header file for the Arria10 SoCDK QSPI U-boot device tree. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* HSD #1508168527-2: arm: socfpga: arria10: Add handoff header for A10 SoCDK ↵Dalon Westergreen2020-07-211-0/+305
| | | | | | | | | | SDMMC Add the qts-filter-a10.sh generated handoff header file for the Arria10 SoCDK SDMMC u-boot device tree. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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