| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| |
|
|
|
|
|
|
|
|
|
| |
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface
Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes in v2
- Remove the change of handoff as our dev kit using DDR3
|
| |
|
|
|
|
|
|
|
| |
To fix the Preloader to ensure the bridges are disabled when
programming the FPGA. The bridge is now enabled upon Reset Manager
initialization but left open even during FPGA programming which is
not safe to do so.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
|
|
|
| |
To fix the broken SDRAM self refresh feature where the
SDRAM content is wiped off after warm reset. The SDRAM
ECC initialization should be skipped when SDRAM self
refresh is enabled and after a warm reset.
Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v2
- Update the comment to reflect the code change
|
| |
|
|
|
|
|
|
|
|
|
| |
To enforce initialization of entire SDRAM ECC bit if SDRAM
ECC is enabled. This is to avoid any HW complication and build
error if incorrect combinations are selected in tools.
Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v2
- Fix spelling error in printout
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
When we tell the compiler to optimize for ARMv7 (and ARMv6 for that
matter) it assumes a default of SCTRL.A being cleared and unaligned
accesses being allowed and fast at the hardware level. We set this bit
and must pass along -mno-unaligned-access so that the compiler will
still breakdown accesses and not trigger a data abort.
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Mans Rullgard <mans@mansr.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
|
|
| |
First of all this looks a lot better, but it also
prevents a gcc warning (W=1), that the weak function
has no previous prototype.
cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
| |
Enable SDRAM ECC overwrite where it occurs when a correctable ECC
error is seen. A new read/modify/write to be scheduled for that
location to clear the ECC error.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
Increase the buffer size to store the DMA microcode. These microcode
are used to initialize the SDRAM ECC bit. The size of microcode
will grow bigger with size of SDRAM.
Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v2
- Fix some grammer in commit message
- Renew the copyright header
- Increase the buffer size for storing the microcode
|
| |
|
|
|
|
|
|
|
| |
This patch fixed the overflow formula in both get_timer_masked
and get_timer_count_masked. This bug can cause QSPI flash failed
to erase and time out intermittent during the process of
erasing.
Signed-off-by: Tien Fong <tfchee@altera.com>
|
| |
|
|
|
|
|
|
|
| |
This patch skips the PLL workaround for ramboot if booting from FPGA, and
adds the preloader generator option CONFIG_PRELOADER_RAMBOOT_PLLRESET to
force the workaround from the preloader if requested by the user, or
configured by editing the configuration.
Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
|
| |
|
|
|
|
|
|
|
| |
Full cache line writes to the same memory region from at least two
processors might deadlock the processor. Exists on r1, r2, r3
revisions.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
|
| |
|
|
|
|
|
|
|
| |
A short loop including a DMB instruction might cause a denial of
service on another processor which executes a CP15 broadcast operation.
Exists on r1, r2, r3, r4 revisions.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
|
| |
|
|
|
|
|
| |
Add common code to enable the workaround for ARM erratum 716044. This
will be enabled for Tegra.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Somehow, ECC was enabled but scrubbing was disabled for our git repo
default board configuration. This patch corrects that issue by setting
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN to 0 for the default configuration,
makes sure CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA is always disabled,
and CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN is also always disabled. Note
that the SDRAM configuration code always sets
CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA and
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN to 0 overriding the preloader
generator handoffs leaving an OS specific driver with the choice of
using those features if needed. The preloader does the basic SDRAM ECC
initialization tasks required for basic ECC initialization and protection.
Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
This patch enhances the previously submitted patch for FogBugz #223741 by
programming the SDRAM protection rules to prevent SDRAM accesses beyond
maximum configured SDRAM. This patch also corrects an issue in the way
SDRAM rows was calculated and configured in that same patch. The number
of rows is set such that 4G of memory is decoded to workaround the
SDRAM errata and limits memory accesses by using the SDRAM range protection
logic to cause a data abort if an access occurs beyond available,
configured memory in the system.
Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
|
| |
|
|
|
|
|
|
|
|
| |
Use linker directives to force certain global variables into .data segment
instead of bss, so bss section is not used prior to u-boot relocation..
Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
---
V3: add more information to commit log
V2: Change emails to opensource emails
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
CONFIG_HPS_RESET_WARMRST_HANDSHAKE_SDRAM
To enable SDRAM self refresh support,
CONFIG_PRELOADER_WARMRST_PRESERVE_SDRAM
and CONFIG_HPS_RESET_WARMRST_HANDSHAKE_SDRAM
should always be set to exactly the same value.
Replacing CONFIG_PRELOADER_WARMRST_PRESERVE_SDRAM
with CONFIG_HPS_RESET_WARMRST_HANDSHAKE_SDRAM
avoided the posibility of making a mistake.
Signed-off-by: Chin Keong Ang <ckang@altera.com>
|
| |
|
|
|
|
|
|
|
|
|
|
| |
When BootSelect is set to zero. The BootRom does almost nothing.
The BootRom does not setup any of the handoff to the preloader,
nor does the BootROM perform any work necessary to handle a warm reset.
This patch fixes the preloader's handling of BootSelect being zero.
When BootSelect is zero, the preloader will not examine any handoff
from the BootRom, and the preloader will execute a full cold reset
startup sequence.
Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com>
|
| |
|
|
|
|
|
|
|
| |
This patch configures the debug clock source according to the handoff from
Quartus.
Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
---
V2: Change email references to opensource emails
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch prevents the SDRAM controller from hanging indeterminately if
a memory read operation is posted to the SDRAM controller beyond the
amount of memory controlled by the SDRAM controller.
Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
---
V5: - Read sdram register and change values back to handoff values
before calculating sdram size
- Add informative message to user about sdram addrorder change
V4: - Remove extra linefeeds, remove references to FBs in source code,
restate commit header again.
V3: - Change emails to opensource emails
V2: - Updates per first Crucible review
- Simplify commit log entry
|
| |
|
|
|
|
|
|
|
|
| |
To enable SDRAM contents preservation over warm reset.
Enable by defining CONFIG_PRELOADER_WARMRST_PRESERVE_SDRAM as 1 in build.h
Once enabled, during warm reset, it will skip resetting SDRAM controller
and skip calibrating SDRAM PHY.
Signed-off-by: Chin Keong Ang <ckang@altera.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
Settings to configure the sdram controller for
when we want to enable ddr self-refresh.
sdr.ctrlcfg.lowpwreq.selfrfshmask = 3
sdr.ctrlcfg.lowpwrtiming.clkdisablecycles = 8
sdr.ctrlcfg.dramtiming4.selfrfshexit = 512
Signed-off-by: Alan Tull <atull@altera.com>
v2: selfrfshmask = 3 instead of 1 to chose all ddr
|
| |
|
|
|
|
|
| |
To update Clock Manager driver to avoid PLL from using external
regulator.At same time, removed double reset code workaround.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
To enable RAM boot when CSEL = 0. The RAM boot code will put
Main PLL and Peripheral to bypass mode. It will set the QSPI
and NANDSDMMC clock dividers for both PLLs to default value.
Later, the code will disable the RAM boot before triggering
warm reset. The RAM boot code is located at the last 4kB of
on-chip RAM. The purpose of this RAM boot is to overcome boot
up hang issue which due to faulty PLL.
Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v2
- Auto calculate the function size when copying the function
|
| |
|
|
|
|
|
| |
To fix the L4 clock calculation algorithm as the L4 divider
in value of power of 2 instead divisor itself.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
| |
To fix the issue where the LWH2F bridge is not enabled per
handoff when boot from FPGA. This will ensure Preloader pass
the bridge handoff info to U-Boot correctly.At same time, this
patch also fixed the label duplication within lowlevel_init.S.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
|
|
| |
To fix the SDRAM PLL phase aligning issue which cause SDRAM
calibration failed. This patch will reset the SDRAM VCO twice
and implemented software de-bouncing check for PLL lock status.
Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v2
- Using udelay instead for loop implementation
|
| |
|
|
|
|
|
|
| |
Enhance U-Boot command console experience by enabling
command line editing. User can use up arrow to retrieve
previous typed command and edit it later on.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
| |
If SDMMC PWREN is used, we need to ensure BootROM always
reconfigure IOCSR and pinmux after warm reset. This is to cater
the use case of board design which is using SDMMC PWREN pins.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
| |
Enhance the U-Boot to configure the L2 address filter. This
is to avoid the dependency of getting Preloader to configure it.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
| |
This change fixes PID toggling so that USB transaction works correctly,
updating the codes so that it conforms to the u-boot standard better, ie.
replacing dwc_write32 with __raw_write. Also replaces infinite loop with
time outs.
Signed-off-by: Tien Hock Loh <thloh@altera.com>
|
| |
|
|
|
|
|
|
|
| |
To ensure the function always return 0 upon completion. This is
to avoid the user impression that the function is hitting error
due to non zero return. At same time, fix the code to enable
back the i-cache and branch predictor after applycfg is applied.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
| |
To fix the Clock Manager driver which currently not configuring
the main_nand_sdmmc_clk as its not used. This patch will enable
user to have both NAND and SDMMC clock from different PLL sources.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enhance the Preloader to have the capability of programming FPGA
from SD card's FAT partition. User just need to put the RBF file
into FAT partition. This is an additional feature on top of
existing Preloader programming FPGA from QSPI flash.
Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v3
- Used puts for prinout without argument
Changes for v2
- Removed debug printf
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enable the DesignWare I2C controller support within U-Boot.
Only I2C0 is enabled per Cyclone V and Arria V dev kit. At
same time, rename socfpga_base_addrs.h to hardware.h. This is
to align with the file name used by DesignWare I2C driver.
Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v4
- Update the license header for hardware.h
Changes for v3
- Renamed socfpga_base_addrs.h to hardware.h
Changes for v2
- Updated hardware.h which mainly used for I2C driver
|
| |
|
|
|
|
|
|
| |
Clear all the PLL lost of lock bits in Clock Manager's interrupt
status register. The false PLL lost of lock happen during the PLL
reconfiguration in Preloader stage.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enhance the drivers for flash controllers (SDMMC and QSPI)
and UART to determine the incoming clock frequency (from PLL)
based on derived values instead of macros.
The derived values are based on Clock Manager registers and incoming
clock source frequencies (from handoff file pll_config.h). This
enhancement will avoid user manually update the clock frequencies
for drivers when any changes made to Clock Manager configuration.
Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v2
- Used uint32_t instead unsigned long for Clock Manager register struct
|
| |
|
|
|
|
|
|
| |
Preloader will display the clock info such as MPU clock, DDR clock
and others during run time. It will help user to know the current
clock configuration being used without reading the handoff file.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
| |
Enhance the Arria V MPU clock from 800MHz to 1050MHz. This is
to align with the new Arria V dev kit which is using I3 speed
grade parts.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
User can optional enable the Preloader to scrub the SDRAM memory
to initialize the SDRAM ECC bits. This is to enable subsequent
software that running on SDRAM enable the SDRAM ECC interrupt.
To do the scrubbing, DMA is used to speed up the scrubbing speed.
At same time, the DMA run in parallel while Preloader loading
the subsequent boot image from flashes.
To scrub the whole 1GB memory, it took 1446ms. As comparison,
scrubbing using processor and memset function is taking 13s.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
|
| |
To add the driver support for DMA PL330 that located within HPS. The
driver does have high level function which enable memory-to-memory,
memory-to-peripheral and peripheral-to-memory transfer. It also
include a memory scrubbing function which write zeroes to
the assigned memory region
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
|
| |
Enhance the fpga2sdram bridge release sequence to support
asymmetric multiprocessing (AMP) use case. The master in FPGA
might sending transaction to fpga2sdram bridge before the bridge
is enabled. This enhancement will ensure the transaction will
be back pressured and continued normally once the bridge is enabled.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
| |
Enhance the semihosting code where we will using different
SVC value for THUMB mode.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
|
| |
Ensure the stack pointer memory region is initialized during the
early run of the Preloader and U-Boot. This is to avoid the false
double bit error which might occurred during stack access. It is
due to the OCRAM controller always read in 64 bits manner. This issue
is spotted when we switch to new Altera version GNU toolchain.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
Enhance Preloader and U-Boot to auto calculate the SDRAM size. This
will save user from the hassle of modifying the PHYS_SDRAM_1 macro
when the SDRAM change. The SDRAM size calculation will based on SDRAM
controller settings such as address row, columns, banks and others.
Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v2
- using macro for SDRAM width with ECC enabled
- fixed the SDRAM size calculation algorithm
|
| |
|
|
|
|
|
|
| |
To fix the build error during the comhination where SDRAM ECC is
disabled and Preloader FAT support is enabled. The SDRAM ECC padding
is not required when the SDRAM ECC is disabled.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
| |
This is to display a message at UART terminal when the watchdog
is enabled. It will remind user the possibility of system reset
caused by watchdog timeout.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Bridge_enable_handoff command is used to enable all the bridges
based on handoff values. It took place after the FPGA programming.
This enhancement will remove all memory display commands as
they will trigger data abort if user press enter many times
after run bridge_enable_handoff.
The data abort is caused by U-Boot memory display features which
will auto increment the address after user press enter later on.
When this happen, the memory display command will display next
address which are not a valid address and causing data abort.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
To enhance the existing SDRAM memory test. Added a memory
test which is utilizing the PRBS (pseudo-random binary sequence)
algorithm. At same time, ensure lowest memory map is mapped to
SDRAM so it can be tested too.
Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v4
- Removed redundant code
Changes for v3
- reshuffled the condition check for coverage within SDRAM test
Changes for v2
- used macro to determine the SDRAM test coverage
- updated comments
|
| |
|
|
|
|
|
|
|
| |
To fix the Preloader FPGA programming issue due to recent
enhancement. This is to avoid programming additional words
into FPGA. At same time, update the FPGA2SDRAM port release
code after the FPGA programming.
Signed-off-by: Chin Liang See <clsee@altera.com>
|
