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authorChee Hong Ang <chee.hong.ang@intel.com>2020-08-11 21:52:30 +0800
committerLey Foon Tan <ley.foon.tan@intel.com>2020-10-09 17:53:17 +0800
commit505dc1c6795ba0b80abf344bb6464cdc20774f44 (patch)
tree594b4ad79961d7b4b3ab4646d004d7e2f96c69eb /.checkpatch.conf
parent269564ccf4b2f3169949dacefa1b5d7e8b40e479 (diff)
downloadu-boot-505dc1c6795ba0b80abf344bb6464cdc20774f44.tar.gz
Makefile: socfpga: Generate sfp file with 4 SPL images
Generate 'u-boot-splx4.sfp' which consist of 4 SPL images required for booting up Cyclone5/Arria10. By default, this 'u-boot-splx4.sfp' is generated without extra padding after each SPL image. For Cyclone5, 'u-boot-splx4.sfp' contains: 4 x SPL(64KB) = 256KB For Arria10, 'u-boot-splx4.sfp' contains: 4 x SPL(256KB) = 1024KB For Cyclone5 using NAND flash image layout for 128 KB memory blocks, user can 'make' the following target to generate 4 SPL images with padding: make u-boot-spl-padx4.sfp 'u-boot-spl-padx4.sfp' contains four 128KB SPL images (each 64KB SPL is followed by 64KB of zero-padding). 4 x (SPL(64KB) + zero-padding(64KB)) = 512KB Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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