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| author | Stefan Roese <sr@denx.de> | 2020-08-24 13:04:39 +0200 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2020-10-07 20:25:57 +0200 |
| commit | fd569c878bb145c5ff55b0f4ecfd9f457d26e178 (patch) | |
| tree | 245fb0025d8d6b079809f21270b9595589115be9 | |
| parent | 92ca2fee08d560bbc1d30a9eb357c862ccdd94c8 (diff) | |
| download | u-boot-fd569c878bb145c5ff55b0f4ecfd9f457d26e178.tar.gz | |
mips: octeon: cpu.c: Add table for selective swapping
Import octeon_should_swizzle_table[] which is needed for the area
specific swapping. It will be used by the platform specific
mangle-port.h header.
Imported from Linux v5.7.
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | arch/mips/mach-octeon/cpu.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c index 2680a2e6ed..6f87a4ef8c 100644 --- a/arch/mips/mach-octeon/cpu.c +++ b/arch/mips/mach-octeon/cpu.c @@ -13,6 +13,27 @@ DECLARE_GLOBAL_DATA_PTR; +/* + * TRUE for devices having registers with little-endian byte + * order, FALSE for registers with native-endian byte order. + * PCI mandates little-endian, USB and SATA are configurable, + * but we chose little-endian for these. + * + * This table will be referened in the Octeon platform specific + * mangle-port.h header. + */ +const bool octeon_should_swizzle_table[256] = { + [0x00] = true, /* bootbus/CF */ + [0x1b] = true, /* PCI mmio window */ + [0x1c] = true, /* PCI mmio window */ + [0x1d] = true, /* PCI mmio window */ + [0x1e] = true, /* PCI mmio window */ + [0x68] = true, /* OCTEON III USB */ + [0x69] = true, /* OCTEON III USB */ + [0x6c] = true, /* OCTEON III SATA */ + [0x6f] = true, /* OCTEON II USB */ +}; + static int get_clocks(void) { const u64 ref_clock = PLL_REF_CLK; |