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| author | Tom Rini <trini@konsulko.com> | 2017-12-11 17:06:04 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-12-11 17:06:04 -0500 |
| commit | 87f3dee22b174aa32db8213a3187aa809859c9e2 (patch) | |
| tree | e0245f9d050e6fed566a9f8d71b0bcacbdb9a004 | |
| parent | 6f1ee8a4bf72d4824cea25849f775ab487ddd579 (diff) | |
| parent | 7f8e75390b9c9b79748b2f87dd7ab45674323d58 (diff) | |
| download | u-boot-87f3dee22b174aa32db8213a3187aa809859c9e2.tar.gz | |
Merge git://git.denx.de/u-boot-uniphier
| -rw-r--r-- | arch/arm/mach-uniphier/clk/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/mach-uniphier/clk/pll-base-ld20.c | 15 | ||||
| -rw-r--r-- | drivers/mtd/nand/Kconfig | 7 |
3 files changed, 14 insertions, 9 deletions
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index 76633bcd49..5cd0897dff 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -27,3 +27,4 @@ endif obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o +obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += pll-base-ld20.o diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c index 3aa42f8bfd..385f54dfc3 100644 --- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c @@ -5,8 +5,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/delay.h> +#include <linux/kernel.h> #include <linux/errno.h> #include <linux/io.h> #include <linux/sizes.h> @@ -18,7 +20,6 @@ #define SC_PLLCTRL_SSC_EN BIT(31) #define SC_PLLCTRL2_NRSTDS BIT(28) #define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0) -#define SC_PLLCTRL3_REGI_SHIFT 16 #define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16) /* PLL type: VPLL27 */ @@ -41,13 +42,17 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, if (freq != UNIPHIER_PLL_FREQ_DEFAULT) { tmp = readl(base); /* SSCPLLCTRL */ tmp &= ~SC_PLLCTRL_SSC_DK_MASK; - tmp |= (487 * freq * ssc_rate / divn / 512) & - SC_PLLCTRL_SSC_DK_MASK; + tmp |= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK, + DIV_ROUND_CLOSEST(487UL * freq * ssc_rate, + divn * 512)); writel(tmp, base); tmp = readl(base + 4); tmp &= ~SC_PLLCTRL2_SSC_JK_MASK; - tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK; + tmp |= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK, + DIV_ROUND_CLOSEST(21431887UL * freq, + divn * 512)); + writel(tmp, base + 4); udelay(50); } @@ -90,7 +95,7 @@ int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) tmp = readl(base + 8); /* SSCPLLCTRL3 */ tmp &= ~SC_PLLCTRL3_REGI_MASK; - tmp |= regi << SC_PLLCTRL3_REGI_SHIFT; + tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); writel(tmp, base + 8); iounmap(base); diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 47ec43500c..78a39abf75 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -10,15 +10,14 @@ config SYS_NAND_SELF_INIT NAND initialization process. config NAND_DENALI - bool "Support Denali NAND controller" + bool select SYS_NAND_SELF_INIT imply CMD_NAND - help - Enable support for the Denali NAND controller. config NAND_DENALI_DT bool "Support Denali NAND controller as a DT device" - depends on NAND_DENALI && OF_CONTROL && DM + select NAND_DENALI + depends on OF_CONTROL && DM help Enable the driver for NAND flash on platforms using a Denali NAND controller as a DT device. |